Abstract: A memory system has a data storage element connected by a first memory read device to a first memory output line and by a second memory read device to a second memory output line. A first and a second decoder are connected to the first and second memory read devices, respectively, to read-out data stored in the storage element in response to read address signals applied to the first and second decoders. A "write" operation is effected on the storage element by a write-in device connected between a data input line and the storage element and energized by a third decoder arranged to respond to a write address signal.

Abstract: A signal generator uses a shift register connected in a feedback loop with selectively operable gates between signal storage elements of the shift register. Non-overlapping clock signals are used to operate the gates to shift digital bits within the shift register and to concurrently operate gates connected to outputs of the shift register to define non-overlapping signal generator output signals.