Patents by Inventor Jeffrey P. Wright

Jeffrey P. Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12265489
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: April 1, 2025
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20250085867
    Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Inventors: Bryan David Kerstetter, Donald M. Morgan, Alan J. Wilson, John David Porter, Jeffrey P. Wright
  • Patent number: 12159039
    Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: December 3, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Bryan David Kerstetter, Donald M. Morgan, Alan J. Wilson, John David Porter, Jeffrey P. Wright
  • Publication number: 20240369632
    Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Kenneth M. Curewitz, Jaime Cummins, John D. Porter, Bryce D. Cook, Jeffrey P. Wright
  • Publication number: 20240303194
    Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
    Type: Application
    Filed: April 3, 2024
    Publication date: September 12, 2024
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 12072381
    Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: August 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth M. Curewitz, Jaime Cummins, John D. Porter, Bryce D. Cook, Jeffrey P. Wright
  • Patent number: 11971820
    Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 30, 2024
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20240125851
    Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 18, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Kenneth M. Curewitz, Jaime Cummins, John D. Porter, Bryce D. Cook, Jeffrey P. Wright
  • Publication number: 20240004814
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 4, 2024
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20230350574
    Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Inventors: Bryan David Kerstetter, Donald M. Morgan, Alan J. Wilson, John David Porter, Jeffrey P. Wright
  • Patent number: 11775460
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: October 3, 2023
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11610613
    Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20230004492
    Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 5, 2023
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20230004507
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 5, 2023
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20220400038
    Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 15, 2022
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11403241
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11397679
    Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11381432
    Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Publication number: 20210280225
    Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).
    Type: Application
    Filed: March 25, 2021
    Publication date: September 9, 2021
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 10978116
    Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans