Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.

Abstract: A method, and corresponding apparatus, of assigning processing resources used to manage transport operations between a first memory cluster and one or more other memory clusters, include receiving information indicative of allocation of a subset of processing resources in each of the one or more other memory clusters to the first memory cluster, storing, in the first memory cluster, the information indicative of resources allocated to the first memory cluster, and facilitating management of transport operations between the first memory cluster and the one or more other memory clusters based at least in part on the information indicative of resources allocated to the first memory cluster.

Abstract: A method and corresponding apparatus of managing transport operations between a first memory cluster and one or more other memory clusters, include receiving, in the first cluster, information related to one or more transport operations with related data buffered in an interface device, the interface device coupling the first cluster to the one or more other clusters, selecting at least one transport operation, from the one or more transport operations, based at least in part on the received information, and executing the selected at least one transport operation.

Abstract: A method and corresponding apparatus of managing transport operations between a first memory cluster and one or more other memory clusters, include selecting, at a clock cycle in the first memory cluster, at least one transport operation destined to at least one destination memory cluster, from one or more transport operations, based at least in part on priority information associated with the one or more transport operations or current states of available processing resources allocated to the first memory cluster in each of a subset of the one or more other memory clusters, and initiating the transport of the selected at least one transport operation.

Abstract: In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection module, integrity of the current segment of the data packet is checked based on the one or more data fields and parameters corresponding to the operation associated with the data packet. At least one data field of the one or more data fields is modified upon detecting an integrity error. The data fields are forwarded to the one or more processing clusters.

Abstract: In a network search processor, configured to handle search requests in a router, a scheduler for scheduling rule matching threads initiated by a plurality of initiating engines is designed to make efficient use of the resources in the network search processor while providing high speed performance. According to at least one example embodiment, the scheduler and a corresponding scheduling method comprise: determining a set of bundles of rule matching threads, each bundle being initiated by a separate initiating engine; distributing rule matching threads in each bundle into a number of subgroups of rule matching threads; assigning the subgroups of rule matching threads associated with each bundle of the set of bundles to multiple scheduling queues; and sending rule matching threads, assigned to each scheduling queue, to rule matching engines according to an order based on priorities associated with the respective bundles of rule matching threads.

Abstract: According to at least one example embodiment, a method and a corresponding accumulator scoreboard for managing bundles of rule matching threads processed by one or more rule matching engines comprise: recording, for each rule matching thread in a given bundle of rule matching threads, a rule matching result in association with a priority corresponding to the respective rule matching thread; determining a final rule matching result, for the given bundle of rule matching threads, based at least in part on the corresponding indications of priorities; and generating a response state indicative of the determined final rule matching result for reporting to a host processor or a requesting processing engine.

Abstract: A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks. The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to different physical memory banks, among the plurality of memory banks, and scheduling the selected subset of access requests, each over a separate access port.

Abstract: According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.

Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.

Abstract: According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.

Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection module, integrity of the current segment of the data packet is checked based on the one or more data fields and parameters corresponding to the operation associated with the data packet. At least one data field of the one or more data fields is modified upon detecting an integrity error. The data fields are forwarded to the one or more processing clusters.

Abstract: In a network search processor, configured to handle search requests in a router, a scheduler for scheduling rule matching threads initiated by a plurality of initiating engines is designed to make efficient use of the resources in the network search processor while providing high speed performance. According to at least one example embodiment, the scheduler and a corresponding scheduling method comprise: determining a set of bundles of rule matching threads, each bundle being initiated by a separate initiating engine; distributing rule matching threads in each bundle into a number of subgroups of rule matching threads; assigning the subgroups of rule matching threads associated with each bundle of the set of bundles to multiple scheduling queues; and sending rule matching threads, assigned to each scheduling queue, to rule matching engines according to an order based on priorities associated with the respective bundles of rule matching threads.

Abstract: According to at least one example embodiment, a method and a corresponding accumulator scoreboard for managing bundles of rule matching threads processed by one or more rule matching engines comprise: recording, for each rule matching thread in a given bundle of rule matching threads, a rule matching result in association with a priority corresponding to the respective rule matching thread; determining a final rule matching result, for the given bundle of rule matching threads, based at least in part on the corresponding indications of priorities; and generating a response state indicative of the determined final rule matching result for reporting to a host processor or a requesting processing engine.

Abstract: In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.