Patents by Inventor Jeffrey Patton

Jeffrey Patton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190385210
    Abstract: A color selection system is described herein that provides a facility for customers to receive color selection assistance for color-related buying decisions. The system divides color space into harmonious groups based on hue, chroma, and saturation whereby every major hue family is represented in each color group. This ensures that complete harmonious palettes can be created to align with every user's color and product preferences, across all brands and product classes. The system also provides software for uploading digital images to profile particular products for color information. This assigns a harmonious color palette to each image. The system also enables product images to be profiled into the system so that users can find products that match their color preferences. The system provides a search facility that enables users to find colors, products, and styleboards that match their design concept, or dynamically build their design concept through their search queries.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 19, 2019
    Inventors: Kristen A. Miller, Teresa D. Marcel, James D. McManis, Maureen Daniek, Laurie Ruegamer, Jon Collette, Lisa Perrone, Joe Cincotta, Jeffrey Patton
  • Patent number: 10387938
    Abstract: A color selection system is described herein that provides a facility for customers to receive color selection assistance for color-related buying decisions. The system divides color space into harmonious groups based on hue, chroma, and saturation whereby every major hue family is represented in each color group. This ensures that complete harmonious palettes can be created to align with every user's color and product preferences, across all brands and product classes. The system also provides software for uploading digital images to profile particular products for color information. This assigns a harmonious color palette to each image. The system also enables product images to be profiled into the system so that users can find products that match their color preferences. The system provides a search facility that enables users to find colors, products, and styleboards that match their design concept, or dynamically build their design concept through their search queries.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: August 20, 2019
    Assignee: STYLYZE LLC
    Inventors: Kristen A. Miller, Teresa D Marcel, James D McManis, Maureen Daniek, Laurie Ruegamer, Jon Collette, Lisa Perrone, Joe Cincotta, Jeffrey Patton
  • Publication number: 20150235389
    Abstract: A color selection system is described herein that provides a facility for customers to receive color selection assistance for color-related buying decisions. The system divides color space into harmonious groups based on hue, chroma, and saturation whereby every major hue family is represented in each color group. This ensures that complete harmonious palettes can be created to align with every user's color and product preferences, across all brands and product classes. The system also provides software for uploading digital images to profile particular products for color information. This assigns a harmonious color palette to each image. The system also enables product images to be profiled into the system so that users can find products that match their color preferences. The system provides a search facility that enables users to find colors, products, and styleboards that match their design concept, or dynamically build their design concept through their search queries.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 20, 2015
    Inventors: Kristen A. Miller, Teresa D. Marcel, James D. McManis, Maureen Daniek, Laurie Ruegamer, Jon Collette, Lisa Perrone, Joe Cincotta, Jeffrey Patton
  • Publication number: 20070085149
    Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 19, 2007
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Simon Chan, Paul Besser, Jeffrey Patton
  • Publication number: 20060267107
    Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.
    Type: Application
    Filed: October 17, 2005
    Publication date: November 30, 2006
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Chiu, Jeffrey Patton, Paul Besser, Minh Ngo
  • Publication number: 20060267087
    Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their suicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
    Type: Application
    Filed: September 15, 2005
    Publication date: November 30, 2006
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert Chiu, Paul Besser, Simon Chan, Jeffrey Patton, Austin Frenkel, Thorsten Kammler, Errol Ryan
  • Publication number: 20050048731
    Abstract: A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate. Deep source/drain junctions are formed in the semiconductor substrate using the sidewall spacer. A siliciding spacer is formed over the sidewall spacer after forming the shallow and deep source/drain junctions. A silicide is formed on the deep source/drain junctions adjacent the siliciding spacer, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the silicide.
    Type: Application
    Filed: September 2, 2003
    Publication date: March 3, 2005
    Inventors: Jeffrey Patton, Mehrdad Mahanpour, Thorsten Kammler, David Brown, Paul Besser, Simon Chan, Austin Frenkel
  • Publication number: 20050006705
    Abstract: A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.
    Type: Application
    Filed: July 7, 2003
    Publication date: January 13, 2005
    Inventors: Robert Chiu, Jeffrey Patton, Paul Besser, Minh Ngo
  • Patent number: D880045
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: March 31, 2020
    Assignee: General Electric Company
    Inventors: Richard Clarkson, Tomislav Stimac, Nicholas Castorano, John Edward Chancey, Jeffrey Patton