Patents by Inventor Jeffrey Pidge Rupley, II

Jeffrey Pidge Rupley, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for predicting multiple branches and performing out-of-order branch resolution
    Patent number: 6477640
    Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: November 5, 2002
    Assignee: Motorola, Inc.
    Inventors: Jeffrey Pidge Rupley, II, Marvin A. Denman, Bradley G. Burgess, David C. Holloway
  • Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers
    Patent number: 6157998
    Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: December 5, 2000
    Assignee: Motorola Inc.
    Inventors: Jeffrey Pidge Rupley, II, Marvin A. Denman, Bradley G. Burgess, David C. Holloway