Abstract: An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

Abstract: An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer.

Abstract: An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa.

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

Abstract: A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.

Abstract: A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.