Abstract: A direct memory access (DMA) controller stores a set of DMA instructions in a list, where each entry in the list includes a bit field that identifies the type of the entry. Based on the bit field, the DMA controller determines whether each DMA instruction is a buffer pointer or a jump pointer. If a DMA instruction is identified as a buffer pointer, the DMA controller transfers data to or from the location specified by the buffer pointer. If a DMA instruction is identified as a jump pointer, the DMA controller jumps to the location in the list specified by the jump pointer. A subset of the list of DMA instructions may be cached, and the DMA controller executes the cache entries sequentially. If a jump pointer is encountered in the cache, the DMA controller flushes the cache and reloads it from main memory based on the jump pointer.

Abstract: A memory controller includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a chip-select-interface type of memory. The SDRAM-interface controller is configured to communicate with one or more SDRAMs. The SDRAM-interface controller provides a plurality of interface signals to the SDRAM via a dedicated port. One of the interface signals, an SDRAM address/control signal, has a dual role. In one role, it serves as an address bit during memory transactions with the SDRAM. In a second role, it serves as a control signal that facilitates the refresh operation of the SDRAM.

Abstract: A memory controller includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a chip-select-interface type of memory. The SDRAM-interface controller is configured to communicate with one or more SDRAMs. The SDRAM-interface controller provides a plurality of interface signals to the SDRAM via a dedicated port. One of the interface signals, an SDRAM address/control signal, has a dual role. In one role, it serves as an address bit during memory transactions with the SDRAM. In a second role, it serves as a control signal that facilitates the refresh operation of the SDRAM.

Abstract: A memory controller includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a chip-select-interface type of memory. The SDRAM-interface controller configured to communicate with one or more SDRAMs. The SDRAM-interface controller provide a plurality of interface signals to the SDRAM via a dedicated port. One of the interface signals, an SDRAM address/control signal, has a dual role. In one role, it serves as an address bit during memory transactions with the SDRAM. In a second role, it serves as a control signal that facilitates the refresh operation of the SDRAM.

Abstract: A memory controller includes a register and an interface circuitry. The register stores read timing-parameters for a memory. The interface circuitry communicates with the memory by providing a plurality of control signals to the memory. The control signals may include a chip-enable signal and a read-enable signal. The interface circuitry uses the read timing-parameters to provide the plurality of control signals. The relative timing of the plurality of control signals to one another depends at least in part on the read timing-parameters. The user can program the read timing-parameters in order to support and facilitate transactions with a variety of memory devices.