Patents by Inventor Jeffrey R. Gemar

Jeffrey R. Gemar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9267989
    Abstract: Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: February 23, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Wei Chen, Yucong Tao, Matthew L. Severson, Jeffrey R. Gemar, Chang Yong Yang
  • Publication number: 20140223250
    Abstract: Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 7, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Wei Chen, Yucong Tao, Matthew L. Severson, Jeffrey R. Gemar, Chang Yong Yang
  • Patent number: 8713388
    Abstract: In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: April 29, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Wei Chen, Yucong Tao, Matthew L. Severson, Jeffrey R. Gemar, Chang Yong Yang
  • Publication number: 20120216089
    Abstract: In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 23, 2012
    Applicant: QUALCOMM Incorporated
    Inventors: Wei Chen, Yucong Tao, Matthew L. Severson, Jeffrey R. Gemar, Chang Yong Yang
  • Patent number: 6765915
    Abstract: A packet communication scheduling system comprises tunnel schedulers, a packet scheduler, and a rate controller. The packet scheduler generates a packet schedule and first-set information in response to packet information. The first tunnel scheduler generates a first schedule for a first set of tunnels in response to the first-set information. The first tunnel scheduler also generates second-set information in response to the first-set information. The second tunnel scheduler generates a second schedule for a second set of tunnels in response to the second-set information. The second tunnel scheduler also generates third-set information in response to the second-set information. The third tunnel scheduler generates a third schedule for a third set of tunnels in response to the third-set information. The third tunnel scheduler selects a next third-set tunnel identifier based on the third schedule.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: July 20, 2004
    Assignee: Conexant Systems, Inc.
    Inventors: Michael M. Metzger, Jeffrey R. Gemar, Uve W. Rick
  • Patent number: 6483839
    Abstract: A traffic manager coupled to a communication system for scheduling transmission of information associated with a plurality of connections in the communication system. The traffic manager includes a priority queue, a connection data structure, and a scheduler. The connection data structure includes a guaranteed bit frame rate field for each connection. The scheduler is coupled to the connection data structure and the priority queue. The scheduler loads information from the data structure to the queue, wherein the scheduler shapes the connection for a minimum cell rate and allows use by the connection of excess bandwidth if the guaranteed bit rate field is set.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: November 19, 2002
    Assignee: Conexant Systems, Inc.
    Inventors: Jeffrey R. Gemar, Warner B. Andrews, Jr.
  • Patent number: 6414963
    Abstract: A traffic manager system is coupled to a communication system for scheduling transmission of data associated with a plurality of connections in the communication system. The traffic manager can include a schedule table, a global priority queue, and a scheduler. The schedule table includes a plurality of slot locations, each having a plurality of tunnel entries. The scheduler is coupled to the schedule table and the global priority queue. The global priority queue has a tunnel level associated with the plurality of tunnel entries of the slot. The scheduler processes the slot locations in the schedule table and sets a tunnel active in response to processing one of the plurality of tunnel entries.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: July 2, 2002
    Assignee: Conexant Systems, Inc.
    Inventor: Jeffrey R. Gemar