Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.

Abstract: In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection module, integrity of the current segment of the data packet is checked based on the one or more data fields and parameters corresponding to the operation associated with the data packet. At least one data field of the one or more data fields is modified upon detecting an integrity error. The data fields are forwarded to the one or more processing clusters.

Abstract: In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection module, integrity of the current segment of the data packet is checked based on the one or more data fields and parameters corresponding to the operation associated with the data packet. At least one data field of the one or more data fields is modified upon detecting an integrity error. The data fields are forwarded to the one or more processing clusters.

Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.

Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.

Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.

Abstract: A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.