Abstract: Compounds and compositions comprising specific metal salts of bicyclo[2.2.1]heptane dicarboxylate salts in order to provide highly desirable properties within polyolefin articles are provided. The inventive salts and derivatives thereof are useful as nucleating and/or clarifying agents for such polyolefin, provide excellent crystallization temperatures, stiffness, and calcium stearate compatibility within target polyolefin. Also, such compounds exhibit very low hygroscopicity and therefore excellent shelf stability as powdered or granular formulations. Polyolefin additive compositions and methods of producing polyolefin with such compounds are also contemplated within this invention.

Abstract: This invention relates to a process for preparing alditol acetals, such as dibenzylidene sorbitols, monobenzylidene sorbitols, and the like, through the reaction of unsubstituted or substituted benzaldehydes with alditols (such as sorbitol, xylitol, and ribitol) in the presence of a mineral acid and at least one surfactant having at least one pendant group of 6 carbon chains in length. Such a reaction provides a cost-effective, relatively safe procedure that provides excellent high yields of alditol acetal product. Furthermore, such a specific reaction is also the best known procedure for the production of certain compounds which can be easily separated from other formed isomers. Additionally, such a procedure facilitates the production of certain asymmetric alditol acetal compounds and compositions in acceptable yields as well. Such alditol acetals are useful as nucleating and clarifying agents for polyolefin formulations and articles, as one example.

Abstract: A computer processor includes a dynamic latency module. The dynamic latency module includes a read-only memory ("ROM") in which is stored a plurality of sets of latency values. The dynamic latency module further includes a register coupled to the ROM and adapted to store at least one set of the plurality of sets of latency values. The dynamic latency module dynamically sets a plurality of memory access latency values by determining an operating speed of the processor and implementing one of the plurality of sets of latency values based on the operating speed.