Abstract: A method of configuring a system includes a selectable analog output device and an analog front end (AFE). The method includes selecting, via a graphical user interface (GUI), an analog output device that provides an analog output signal, the selected device having predetermined characteristics. The method further includes selecting an operating condition for the system and a performance criterion for the system. The method also includes providing a configuration value for programming the AFE based on the selected operating condition and performance criterion.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design requirements indicative of desired power supply designs; query the database for components that satisfy the design requirements; determine a plurality of power supply designs in accordance with the components and the design parameters; determine key parameters of at least a subset of the determined power supply designs; and rank the power supply designs.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design parameters indicative of a plurality of loads of a multiple-load device; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design parameters indicative of a plurality of loads of a multiple-load device; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design parameters indicative of characteristics of an LED lighting solution; determine a plurality of LED lighting array designs, each design including at least one of a parallel and a series arrangement of LEDs and configured to provide an amount of light specified by the design parameters; for each one of at least a subset of the plurality of LED lighting array designs, determine an LED driver design configured to power the one of the LED lighting array designs; and generate at least one LED lighting solution, each LED lighting solution including one of the LED lighting array designs combined with one of the LED driver designs configured to power the one of the LED lighting arrays.

Abstract: A sender, such as a sales representative, may create a customized product notice message directly from a web site that is then sent to one or more customers. The customized product notice message may contain information, such as URL links, that relate to the product. The product notice message may also be customized to include items such as the sender's company logo and the like. When the user opens the product notice message a tracking message is automatically sent to the user who created the message. The user's activity relating to the content of the message that may be tracked is stored within a data store. This activity data may then be delivered to the sender at predetermined times.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design requirements indicative of desired power supply designs; query the database for components that satisfy the design requirements; determine a plurality of power supply designs in accordance with the components and the design parameters; determine key parameters of at least a subset of the determined power supply designs; and rank the power supply designs.

Abstract: A process for preparing a light-sensitive integrated circuit (IC) for packaging that provides a reduced exposure of the light-sensitive IC to light. The process includes providing a semiconductor substrate (e.g., a silicon wafer) with a plurality of light-sensitive ICs formed in/on its upper surface. The lower surface is optionally coated with opaque material. Next, the semiconductor substrate is diced to form individual light-sensitive ICs, each of which has a semiconductor substrate lower surface and semiconductor substrate lateral edges. The semiconductor substrate lateral edges (and optionally backside) are then spray coated with an opaque material (e.g., opaque ink) to form an opaque layer covering the semiconductor substrate lateral edges. The opaque layer prevents light from entering the semiconductor substrate through the lateral edges and interfering with the operation of the light-sensitive IC.

Abstract: The present invention provides a “built-in” wave dampening, antireflective thin-film layer in a copper dual damascene film stack that reduces the standing wave intensity in the deep-UV photoresist. This is accomplished by depositing optically customized silicon/oxide/nitride films during dual damascene processing. In particular, one or more silicon nitride layers are replaced with a light absorbing silicon oxynitride film to provide built-in dampening layers. The silicon oxynitride stack can be densified by heat treatments to minimize electrical leakage concerns, if any. The invention eliminates the need for adding extra thin-film stacks during deep-UV photoprocessing.

Abstract: An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.

Abstract: There is disclosed herein a technique for manufacturing a group of memory cells or devices on a common oxide coated silicon substrate such that the cells are arranged in rows and columns with row and column spaces separating the individual cells from one another. Each of the cells includes an array of different layers on the oxide coated top surface of the substrate including, in particular, the polysilicon layer. As disclosed, a method is provided for preventing the formation of polysilicon stringers between individual cells during their manufacture. This method is carried out by first forming the columns before the rows are formed such that continuous sidewalls of the columns are exposed to the ambient surroundings. Thereafter, these sidewalls are coated with protective layers, specifically layers of nitride.

Abstract: In the manufacture of memory cells, horizontal etching is controlled in a manner which prevents the formation of stringers between adjacent cells without undercutting the sidewalls of a memory cell.