Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

Abstract: Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.

Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

Abstract: A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

Abstract: Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.

Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

Abstract: Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.

Abstract: A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

Abstract: In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

Abstract: An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

Abstract: A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

Abstract: A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.

Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.