Abstract: A method of designing and manufacturing a modular integrated circuit for a 4 bit microcomputer family utilizing a modular concept which is adaptable for a variety of applications and specific circuit desgins. The modular circuit is designed as a large block of cells which contains an ALU, instruction decoder, bus structure and a small amount of RAM and ROM as well as ROM control logic. In addition, the block contains attachment points for additional ROM and RAM and for special input/output devices such as I/O bus, timekeeping, A-D, D-A, display drive, communication ports and general purpose control lines.

Abstract: A memory mapped I/O scheme treats each I/O buffer as a memory element which can be addressed, written into or read from. Each I/O buffer has its own memory address decoder which eliminates the need for special select/control lines for each buffer and enables the use of a single address/data bus. Thus redesign and reconfiguration of the I/O buffers is more easily accomplished because it does not require new select/control lines to be laid out when buffer locations are changed.

Abstract: A method and apparatus for producing near constant duty cycle over a wide range operating voltage by connecting clamping transistors across critical timing capacitors so as to eliminate undesirable charge injection in MOS and CMOS oscillator systems. In an oscillator in which two inverters are cross-coupled through timing capacitors, each timing capacitor is shunted by a clamping transistor controlled by the output from one of the inverters. The oscillator may be used in a hand-held calculator.

Abstract: A calculator having constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved.