Abstract: Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that, if the first scan chain is operative in the normal mode, inputs are provided to the flip-flops in sequential order with a first of the flip-flops receiving an input prior to a second of the flip-flops, and, if the first scan chain is operative in the rotate mode, inputs are provided to the flip-flops with the first of the flip-flops receiving an input subsequent to the second of the flip-flops.

Abstract: A test system includes a circuit assembly having an IC and an external circuit. The IC comprises test circuitry used to observe data indicative of target resistances in the external circuit. The test system evaluates the data to determine target resistance values. A first embodiment measures two output voltages responsive to a time varying reference voltage. The two output voltages can be used to determine resistance values in the external circuit. A second embodiment enables logic contention on the IC, controllably fixes a pull-down element on the IC, and controllably sweeps a pull-up element on the IC until the voltage at a node between the pull-down and pull-up elements and coupled to an external circuit exceeds a reference voltage.

Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

Abstract: An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN—CLOCK—OUT) at the clock output, determining a delay by calculating the difference between TSCAN—CLOCK—OUT and TCLOCK—OUT, and compensating for the delay by increasing the clock frequency during scan test.

Abstract: Systems and methods for testing integrated circuits (ICs) are provided. In this regard, a representative method involves an IC having a first pad configured as a signal interface for components external to the IC, the first pad having a first receiver configured to receive an input signal from a component external to the IC. The method comprises: electrically interconnecting automated test equipment (ATE) with the IC; providing at least one stimulus such that the IC detects a presence of a signal short between the first pad and the second pad; and receiving information corresponding to the signal short.

Abstract: Systems and methods for designing integrated circuits (ICs) are provided. A representative method includes: providing a netlist; determining components required to implement test of at least a portion of the integrated circuit defined by the netlist; provide a revised netlist including the components determined; and performing a place and route operation with respect to the revised netlist.

Abstract: Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that, if the first scan chain is operative in the normal mode, inputs are provided to the flip-flops in sequential order with a first of the flip-flops receiving an input prior to a second of the flip-flops, and, if the first scan chain is operative in the rotate mode, inputs are provided to the flip-flops with the first of the flip-flops receiving an input subsequent to the second of the flip-flops.

Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

Abstract: A method and apparatus for testing an integrated circuit interconnect comprises an IC having circuitry embedded in the IC capable of providing a pseudo time domain reflectometry test by launching a test transition onto the interconnect and capturing a reflection of the test transition.

Abstract: A scan test architecture is implemented. The scan test architecture provides a method of performing scan test of unbalanced scan chains. The scan test architecture generates a control signal (i.e., masking signal) to mask bits in an unbalanced scan chain. In one embodiment, the control signal is generated with a logic gate, a comparator, and a counter.

Abstract: A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), comprises an IC logic element, a scan chain, and a calibration circuit comprising a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.

Abstract: An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN—CLOCK—OUT) at the clock output, determining a delay by calculating the difference between TSCAN—CLOCK—OUT and TCLOCK—OUT, and compensating for the delay by increasing the clock frequency during scan test.

Abstract: Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.