Abstract: An apparatus for programming selected entries in an address filter table allows dynamic updating of address registers and eliminates the need to disable unmodified registers in arrangements including multiple registers or entries. The apparatus comprises an interface for receiving data frames from a remote station. A media access controller is provided with an address filter table capable of storing a plurality of entries. Each entry includes an address field for storing a predetermined target address, and an enable field for indicating whether or not the entry is valid. The media access controller is configured to receive each of the data frames from the interface. The media access controller examines the enable field of each entry in the address filter table to determine whether or not the entry is valid. The received data frames are then routed to a destination address based upon the target addresses stored in the address filter table.

Abstract: A network interface in a workstation computer includes a pattern matching circuit to enable the workstation computer to wake up to perform prescribed operations requested by a remote workstation. The pattern recognition circuit includes a pattern memory configured for storing a pattern entry for at least a portion of a predetermined pattern. The pattern entry includes a pattern data field and a second field specifying a number of bytes in the input data stream to be ignored prior to comparison with the pattern data field. The pattern matching circuit also includes a comparator for comparing the pattern data field with a selected group of bytes from the data stream. Pattern match logic determines whether the received data packet includes the predetermined pattern based on the comparison result.

Abstract: A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.

Abstract: A network interface for a workstation having multiple power supply domains includes a wake up module for detecting a wake up request in a received data packet according to the on-now power management scheme and Magic Packet.TM. power management schemes. An EEPROM supplies an override bit to ensure that the on-now power management schemes and Magic Packet.TM. power up management schemes can have co-existent detection mechanisms, independent of whether a required enable bit is set by the operating system. The disclosed arrangement maintains the power management schemes in the event that a power loss disables the enabled bit normally supplied by the host computer operating system.

Abstract: A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles.

Abstract: A network interface stores data frames between a host computer and a network in a buffer memory. The network interface stores data frames received from the host computer via a peripheral component interconnect (PCI) bus in a transmit buffer for transmission on the network. The network interface also stores data from the network in a receive buffer for transfer to a host computer memory via the PCI bus. A priority control selectively allocates host computer resources based on network transmission and network reception by the network interface, and based on available space in the receive buffer, available data in the transmit buffer, and the estimated length of data packets received from the network. The selective allocation of host computer resources minimizes transmit buffer underflow and receive buffer overflow.