Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: A Compute Express Link™ (CXL) over Ethernet (COE) station is provided to bridge a CXL fabric and an Ethernet network to allow for efficient native memory load/store access to remotely connected resources. The COE station supports CXL and Ethernet traffic through its CXL interface, scheduler/packers, decoders, VOQs and VIQs by adding COE tags to Ethernet frames. In CXL controller mode, the CXL controller drives the VOQs. In Ethernet mode, the COE module drives the VOQs, and interacts with the MAC sublayer and the PMA sublayer, which are responsible for encoding and decoding data signals for transmission through a serializer/deserializer.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.

Abstract: Various embodiments provide for a multi-channel memory interface capable of supporting a multi-channel memory module (e.g., DIMM) that combines different memory types, such as DDR4/DDR5, DDR5/LPDDR5, or LPDDR4/LPDDR5, through a single physical layer (PHY) interface.

Abstract: A method and system in accordance with the present invention provides for a method and circuit for oversampling using a delay element in which input clock signals and input data signals are affected by phase and time delays to provide for the circuit generating samples providing a greater granularity of detail over a period, thereby reducing error probabilities.

Abstract: In a bus interface unit, a first communications interface is provided for the coupling of a first plurality of peripheral devices of different device types to facilitate communication with a selected one of the first plurality of peripheral devices of different device types. In addition, a second communications interface is provided for coupling to a first bus of an integrated circuit (IC) to facilitate communication with a selected one of a second plurality of devices of the IC, via the first bus. A controller is provided for the coupling of the first and second communications interfaces to facilitate communications between selected ones of the first and second plurality of devices, dynamically selecting and employing a communication protocol consistent with the device type of the selected one of the first plurality of peripheral devices. The bus interface unit has particular application to interfacing external devices with the core of an SOC.

Abstract: A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The current through a first MOS transistor is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source is connected to a reference voltage. The first MOS transistor has the standard threshold implantation but not the threshold voltage reticle option. The current through a second MOS transistor is measured by forcing the same test voltage on the drain and the gate. The gate and said drain of the second MOS transistor are connected together while the source is connected to a reference voltage. The second MOS transistor has the standard threshold voltage implantation and the threshold voltage implantation reticle option layer.

Abstract: In a bus interface unit, a first communications interface is provided for the coupling of a first plurality of peripheral devices of different device types to facilitate communication with a selected one of the first plurality of peripheral devices of different device types. In addition, a second communications interface is provided for coupling to a first bus of an integrated circuit (IC) to facilitate communication with a selected one of a second plurality of devices of the IC, via the first bus. A controller is provided for the coupling of the first and second communications interfaces to facilitate communications between selected ones of the first and second plurality of devices, dynamically selecting and employing a communication protocol consistent with the device type of the selected one of the first plurality of peripheral devices. The bus interface unit has particular application to interfacing external devices with the core of an SOC.

Abstract: In an integrated circuit, a memory unit includes a first and a second data transfer interface. The first data interface services successive first accesses by a processor and subsystem of the IC, whereas the second data interface services second accesses by at least the processor in parallel. In one embodiment, the accesses are properly sequenced and responded to.

Abstract: Described is a method for verification of proper address generation in packet based memory protocol (Direct RDRAM) devices during the auto-refresh or self-refresh cycle that does not require changes to the interface logic or core signal generation. The method requires minimal additional logic while using the core control signals that function similarly to the RAS, CAS, and WE signals in a standard DRAM. Initially, high level (1) data are written to all of the memory cells of one bit line. The signals are manipulated, and a refresh is performed. As each memory cell is addressed during the refresh, the data are changed to a low level (0). Addressing is then verified by observing the data stored in the memory cells and confirming that a low level (0) is now stored. The method may be extended to standard DRAM devices.

Abstract: A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., ⅛, ¼, ½, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of ⅛th of the self-refresh cycle, the activation of the second most significant bit signals completion of ¼th of the self-refresh cycle, the activation of the most significant bit signals completion of ½ of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.

Abstract: The present invention provides an input receiver in a differential amplifier or modified differential amplifier configuration which adjusts the input high and low voltage signals compatible with multiple input/output (I/O) interfaces, including transistor-transistor logic (TTL), Low Voltage TTL (LVTTL), and Stub Series Terminated Logic (SSTL) interfaces. Transistors in a differential amplifier or modified differential amplifier configuration that receive a reference.sub.-- voltage signal and receiver.sub.-- enable signal are adjusted in accordance to the input high signal and input low signal requirements for a selected type of interface, while other transistors remain at a relatively constant voltage. Once a particular type of interface has been selected, the gate voltages for the transistors that receive the reference.sub.-- voltage and receiver.sub.-- enable signals remain relatively constant.

Abstract: A regulator system for an on-chip-generated supply voltage includes a voltage detection circuit, a power-up mode detection circuit, a normal mode detection path, and a power-up detection path. The voltage detection circuit monitors the on-chip-generated supply voltage and generates a signal that indicates the level of this supply voltage. The power-up mode detection circuit detects when the chip is in the power-up mode and generates a path select signal. The path select signal causes the regulator system to select the power-up detection path during the power-up mode and to select the normal detection path when not in the power-up mode. The power-up detection path includes voltage regulation circuitry that does not rely on a reference voltage. In one embodiment, the power-up detection path includes a logic gate coupled to receive the signal from the voltage detector. The logic gate is skewed to have a trip point that corresponds to voltage level slightly greater than that of the external supply voltage.

Abstract: The present invention provides an input receiver that slows the signal fluctuation by limiting the amount of electrical currents flowing through the input receiver. The limiting of electrical current flowing through the input receiver slows the input signal of the receiver which in effect filters out some level of glitches of an input signal. In one embodiment, the input receiver is constructed and implemented in a structure similar to a differential amplifier for a single interface. In another embodiment, the input receiver is constructed and implemented in a modified differential amplifier for a single interface. In a further embodiment, the input receiver is constructed and implemented in a modified differential amplifier for multiple interfaces.

Abstract: A circuit for disabling a two-phase charge pump includes a pump select circuit and a disable control circuit. The pump select circuit is configured to select one control signal from a plurality of control signals in response to at least one select signal. The selected signal is in effect provided to the disable control circuit, which also receives a pump disable signal. A voltage sensing circuit asserts the pump disable signal when the pumped voltage reaches a predetermined maximum level. While the pump disable signal is de-asserted, the disable control circuit in effect provides the selected signal to the two-phase charge pump as a pump control signal. However, when the pump disable signal is asserted, the disable control signal latches the current logic level of the pump control signal so that the pump control signal does not transition while the pump disable signal is asserted.