Patents by Inventor Jeffrey S. Leal
Jeffrey S. Leal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9508689Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: GrantFiled: September 30, 2015Date of Patent: November 29, 2016Assignee: Invensas CorporationInventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, De Ann Eileen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. Del Rosario, John R. Bray
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Patent number: 9490230Abstract: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.Type: GrantFiled: September 28, 2015Date of Patent: November 8, 2016Assignee: Invensas CorporationInventor: Jeffrey S. Leal
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Publication number: 20160027761Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: ApplicationFiled: September 30, 2015Publication date: January 28, 2016Applicant: INVENSAS CORPORATIONInventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, De Ann Eileen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. Del Rosario, John R. Bray
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Publication number: 20160020188Abstract: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.Type: ApplicationFiled: September 28, 2015Publication date: January 21, 2016Applicant: INVENSAS CORPORATIONInventor: Jeffrey S. Leal
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Patent number: 9196588Abstract: An EMI shield can be formed directly on a component, e.g., an unpackaged or packaged semiconductor die, by depositing and curing a curable composition which includes electrically conductive particles and a carrier. In examples, the shield can be configured as a grid or net of electrically conductive traces or lines. The curable electrically conductive material may be applied to the component surface in a flowable form and cured or allowed to cure to form the electrically conductive shield. The shield can be electrically coupled to contacts on an underlying circuit panel or support. The coupling material may be a conductive adhesive, and may be or may include a material the same as, or similar to, the shield material.Type: GrantFiled: November 5, 2012Date of Patent: November 24, 2015Assignee: Invensas CorporationInventor: Jeffrey S. Leal
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Patent number: 9153517Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: GrantFiled: May 17, 2011Date of Patent: October 6, 2015Assignee: Invensas CorporationInventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, DeAnn Eileen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. del Rosario, John R. Bray
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Patent number: 9147583Abstract: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.Type: GrantFiled: October 27, 2010Date of Patent: September 29, 2015Assignee: Invensas CorporationInventor: Jeffrey S. Leal
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Publication number: 20150056753Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.Type: ApplicationFiled: September 8, 2014Publication date: February 26, 2015Applicant: INVENSAS CORPORATIONInventors: Keith Lake Barrie, Suzette K. Pangrle, Grant Villavicencio, Jeffrey S. Leal
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Patent number: 8912661Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.Type: GrantFiled: November 4, 2010Date of Patent: December 16, 2014Assignee: Invensas CorporationInventors: Scott McGrath, Jeffrey S. Leal, Ravi Shenoy, Loreto Cantillep, Simon McElrea, Suzette K. Pangrle
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Patent number: 8829677Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.Type: GrantFiled: September 23, 2011Date of Patent: September 9, 2014Assignee: Invensas CorporationInventors: Keith Lake Barrie, Suzette K. Pangrie, Grant Villavicencio, Jeffrey S. Leal
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Patent number: 8680687Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support.Type: GrantFiled: June 23, 2010Date of Patent: March 25, 2014Assignee: Invensas CorporationInventors: Reynaldo Co, Grant Villavicencio, Jeffrey S. Leal, Simon J. S. McElrea
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Publication number: 20120248607Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.Type: ApplicationFiled: September 23, 2011Publication date: October 4, 2012Applicant: VERTICAL CIRCUITS, INC.Inventors: Keith Lake Barrie, Suzette K. Pangrle, Grant Villavicencio, Jeffrey S. Leal
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Publication number: 20120119385Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: ApplicationFiled: May 17, 2011Publication date: May 17, 2012Applicant: VERTICAL CIRCUITS, INC.Inventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, DeAnn Elleen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. del Rosario, John R. Bray
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Patent number: 8159053Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.Type: GrantFiled: September 28, 2010Date of Patent: April 17, 2012Assignee: Vertical Circuits, Inc.Inventors: Lawrence Douglas Andrews, Jr., Jeffrey S. Leal, Simon J. S. McElrea
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Publication number: 20110272825Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.Type: ApplicationFiled: November 4, 2010Publication date: November 10, 2011Applicant: Vertical Circuits, Inc.Inventors: Scott McGrath, Jeffrey S. Leal, Ravi Shenoy, Loreto Cantillep, Simon J. S. McElrea, Suzette K. Pangrle
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Publication number: 20110266684Abstract: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.Type: ApplicationFiled: October 27, 2010Publication date: November 3, 2011Applicant: Vertical Circuits, Inc.Inventor: Jeffrey S. Leal
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Publication number: 20110012246Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Applicant: Vertical Circuits, Inc.Inventors: Lawrence Douglas Andrews, JR., Jeffrey S. Leal, Simon J.S. McElrea
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Publication number: 20100327461Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support.Type: ApplicationFiled: June 23, 2010Publication date: December 30, 2010Applicant: Vertical Circuits, Inc.Inventors: Reynaldo Co, Grant Villavicencio, Jeffrey S. Leal, Simon J.S. McElrea
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Publication number: 20100140811Abstract: An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.Type: ApplicationFiled: December 9, 2009Publication date: June 10, 2010Applicant: Vertical Circuits, Inc.Inventors: Jeffrey S. Leal, Scott McGrath, Suzette K. Pangrle
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Publication number: 20090206458Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.Type: ApplicationFiled: August 27, 2008Publication date: August 20, 2009Applicant: VERTICAL CIRCUITS, INC.Inventors: LAWRENCE DOUGLAS ANDREWS, JR., JEFFREY S. LEAL, SIMON J.S. McELREA