Patents by Inventor Jeffrey S. LEIB
Jeffrey S. LEIB has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961767Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.Type: GrantFiled: October 17, 2022Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Jeffrey S. Leib, Srijit Mukherjee, Vinay Bhagwat, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 11955532Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.Type: GrantFiled: October 26, 2020Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 11948997Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.Type: GrantFiled: April 17, 2023Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Subhash M. Joshi, Jeffrey S. Leib, Michael L. Hattendorf
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Publication number: 20230261089Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.Type: ApplicationFiled: April 17, 2023Publication date: August 17, 2023Inventors: Subhash M. JOSHI, Jeffrey S. LEIB, Michael L. HATTENDORF
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Publication number: 20230207466Abstract: Embodiments include semiconductor devices. In an embodiment, a semiconductor device comprises a first non-planar transistor over a substrate and a second non-planar transistor over the substrate and parallel to the first non-planar transistor. In an embodiment, a gate structure is over the first non-planar transistor and the second non-planar transistor. In an embodiment, a power rail is between the first non-planar transistor and the second non-planar transistor. In an embodiment, a top surface of the power rail is below a top surface of a gate structure.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Leonard P. GULER, Jeffrey S. LEIB, Chanaka D. MUNASINGHE, Charles H. WALLACE, Tahir GHANI, Mohit K. HARAN
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Patent number: 11664439Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.Type: GrantFiled: April 28, 2021Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Subhash M. Joshi, Jeffrey S. Leib, Michael L. Hattendorf
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Publication number: 20230143021Abstract: Integrated circuit interconnect structure compatible with single damascene techniques and that includes a non-copper via comprising metal(s) of low resistivity that can be deposited at low temperature in a manner that also ensures good adhesion. Metal(s) suitable for the non-copper via may have BCC crystallinity that can advantageously template favorable crystallinity within a diffusion barrier of the upper-level interconnect feature, further reducing electrical resistance of an interconnect structure.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Applicant: Intel CorporationInventors: Daniel B. OBrien, Jeffrey S. Leib, James Y. Jeong, Chia-Hong Jan, Peng Bai, Seungdo An, Pavel S. Plekhanov, Debashish Basu
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Publication number: 20230042218Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.Type: ApplicationFiled: October 17, 2022Publication date: February 9, 2023Inventors: Jeffrey S. LEIB, Srijit MUKHERJEE, Vinay BHAGWAT, Michael L. HATTENDORF, Christopher P. AUTH
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Patent number: 11508626Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.Type: GrantFiled: October 12, 2020Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Jeffrey S. Leib, Srijit Mukherjee, Vinay Bhagwat, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 11482611Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.Type: GrantFiled: November 20, 2020Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 11342445Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.Type: GrantFiled: July 1, 2020Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
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Publication number: 20220093597Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Daniel G. OUELLETTE, Daniel B. O'BRIEN, Jeffrey S. LEIB, Orb ACTON, Lukas BAUMGARTEL, Dan S. LAVRIC, Dax M. CRUM, Oleg GOLONZKA, Tahir GHANI
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Publication number: 20210249524Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.Type: ApplicationFiled: April 28, 2021Publication date: August 12, 2021Inventors: Subhash M. JOSHI, Jeffrey S. LEIB, Michael L. HATTENDORF
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Patent number: 11088261Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.Type: GrantFiled: July 11, 2019Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Subhash M. Joshi, Jeffrey S. Leib, Michael L. Hattendorf
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Patent number: 11063151Abstract: Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.Type: GrantFiled: March 30, 2017Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Jeffrey S. Leib, Daniel B. Bergstrom, Christopher J. Wiegand
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Patent number: 11018222Abstract: Disclosed herein are structures, methods, and assemblies related to metallization in integrated circuit (IC) structures. For example, in some embodiments, an IC structure may include a first nanowire in a metal region and a second nanowire in the metal region. A distance between the first nanowire and the second nanowire may be less than 5 nanometers, and the metal region may include tungsten between the first nanowire and the second nanowire.Type: GrantFiled: December 27, 2019Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Daniel B. O'Brien, Christopher J. Wiegand, Lukas M. Baumgartel, Oleg Golonzka, Dan S. Lavric, Daniel B. Bergstrom, Jeffrey S. Leib, Timothy Michael Duffy, Dax M. Crum
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Publication number: 20210091206Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.Type: ApplicationFiled: November 20, 2020Publication date: March 25, 2021Inventors: Byron HO, Steven JALOVIAR, Jeffrey S. LEIB, Michael L. HATTENDORF, Christopher P. AUTH
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Patent number: 10957782Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.Type: GrantFiled: December 30, 2017Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Subhash M. Joshi, Jeffrey S. Leib, Michael L. Hattendorf
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Publication number: 20210043520Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.Type: ApplicationFiled: October 12, 2020Publication date: February 11, 2021Inventors: Jeffrey S. LEIB, Srijit MUKHERJEE, Vinay BHAGWAT, Michael L. HATTENDORF, Christopher P. AUTH
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Publication number: 20210043754Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Inventors: Jeffrey S. LEIB, Jenny HU, Anindya DASGUPTA, Michael L. HATTENDORF, Christopher P. AUTH