Patents by Inventor Jeffrey Salvacion SOLAS

Jeffrey Salvacion SOLAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942407
    Abstract: In some examples a method comprises forming an insulating member over a circuit on a device side of a semiconductor die, removing a portion of the insulating member to produce a cavity, and forming a seed layer on the insulating member and within the cavity. In addition, the method includes forming a conductive member on the seed layer in the cavity, wherein the conductive member comprises a plurality of layers of different metal materials. Further, the method includes removing the seed layer from atop the insulating member, outside the cavity, after forming the conductive member in the cavity such that a remaining portion of the seed layer is positioned between the conductive member and the insulating member.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Salvacion Solas, Maricel Fabia Escaño
  • Publication number: 20240006351
    Abstract: A described example includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame, the lead frame comprising conductive leads spaced from the die pad; a conductor layer overlying the device side surface; bond pads including bond pad conductors formed in the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer; conductor traces formed in the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer; bond wires bonded to the bond pads electrically coupling the bond pads to conductive leads; and mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Katleen Fajardo Timbol, Jeffrey Salvacion Solas
  • Publication number: 20230068086
    Abstract: In some examples a method comprises forming an insulating member over a circuit on a device side of a semiconductor die, removing a portion of the insulating member to produce a cavity, and forming a seed layer on the insulating member and within the cavity. In addition, the method includes forming a conductive member on the seed layer in the cavity, wherein the conductive member comprises a plurality of layers of different metal materials. Further, the method includes removing the seed layer from atop the insulating member, outside the cavity, after forming the conductive member in the cavity such that a remaining portion of the seed layer is positioned between the conductive member and the insulating member.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Jeffrey Salvacion SOLAS, Maricel Fabia ESCAÑO