Patents by Inventor Jeffrey Schulz

Jeffrey Schulz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11101930
    Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 24, 2021
    Assignee: Altera Corporation
    Inventor: Jeffrey Schulz
  • Publication number: 20200059318
    Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventor: Jeffrey Schulz
  • Patent number: 10491333
    Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: November 26, 2019
    Assignee: Altera Corporation
    Inventor: Jeffrey Schulz
  • Publication number: 20170310340
    Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.
    Type: Application
    Filed: July 13, 2017
    Publication date: October 26, 2017
    Inventor: Jeffrey Schulz
  • Patent number: 9735778
    Abstract: Input-output (IO) circuitry for optimizing power management on an integrated circuit is disclosed. The IO circuitry includes monitoring circuitry and a multiplexer circuit that is controlled by the monitoring circuitry. The monitoring circuitry determines whether majority of the bits of an IO signal are transitioning from a first logical state to a second logical state. When a number of bit transitions of the IO signal exceeds a predetermined bit transition threshold, the monitoring circuitry may send a monitoring circuitry output to the multiplexer circuit to selectively couple an output signal to either the IO signal or an inverted IO signal. The IO circuitry further includes an additional multiplexer that receives the monitoring circuitry output and a clock signal. The additional multiplexer selects an additional output signal from the monitoring circuitry output and the clock signal based on a control signal that indicates a power-savings operation.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: August 15, 2017
    Inventor: Jeffrey Schulz
  • Patent number: 9712186
    Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: July 18, 2017
    Assignee: Altera Corporation
    Inventor: Jeffrey Schulz
  • Patent number: 9558131
    Abstract: An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 31, 2017
    Assignee: Altera Corporation
    Inventors: Jeffrey Schulz, Chiakang Sung, Michael H. M. Chu
  • Patent number: 9424073
    Abstract: Techniques and mechanisms handle transactions between various components of a memory controller. For example, a memory controller may include a component implemented in configurable logic and another component implemented in hard logic.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: August 23, 2016
    Assignee: Altera Corporation
    Inventor: Jeffrey Schulz
  • Patent number: 9343124
    Abstract: A method and system for operating a multi-port memory system are disclosed. A memory controller may service read requests by accessing requested data from an external memory and communicating it to the requesting memory ports for access by devices coupled to the memory ports. A shared memory of the memory controller may be used to temporarily store data if a buffer associated with a requesting device is full. To reduce the ability for a slower memory port to occupy the shared memory and cause faster memory ports to be underserviced, the memory controller may advantageously regulate or limit issuance of read requests by memory ports operating at slower clock frequencies. The memory ports may be regulated independently of one another based on at least one respective attribute of each memory port, at least one attribute of the external memory, etc.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: May 17, 2016
    Assignee: Altera Corporation
    Inventors: Caroline Ssu-Min Chen, Jeffrey Schulz, Michael H. M. Chu, Ravish Kapasi
  • Patent number: 9276582
    Abstract: A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: March 1, 2016
    Assignee: Altera Corporation
    Inventors: Jeffrey Schulz, Michael Hutton
  • Patent number: 9244867
    Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have predetermined bit widths. To provide the memory controller with adjustable port widths, a mapping interface may be provided that interfaces between master processing modules and the memory controller. The mapping interface may allocate port resources such as read data ports and write data ports of the memory controller to each master processing module. The mapping interface may assign a desirable number of read data ports and write data ports to each master to accommodate the requirements of that master. The mapping interface may assign a command port to each master that receives memory access requests from that master. The mapping interface may convey write acknowledgements in response to fulfilling write access requests.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: January 26, 2016
    Assignee: Altera Corporation
    Inventors: Jeffrey Schulz, Ching-Chi Chang, Caroline Ssu-Min Chen
  • Patent number: 9208109
    Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: December 8, 2015
    Assignee: Altera Corporation
    Inventors: Michael H. M. Chu, Jeffrey Schulz, Chiakang Sung, Ravish Kapasi
  • Publication number: 20150341037
    Abstract: A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.
    Type: Application
    Filed: July 6, 2015
    Publication date: November 26, 2015
    Inventors: Jeffrey Schulz, Michael Hutton
  • Patent number: 9077338
    Abstract: A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 7, 2015
    Assignee: ALTERA CORPORATION
    Inventors: Jeffrey Schulz, Michael Hutton
  • Patent number: 9032162
    Abstract: An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventors: Ching-Chi Chang, Ravish Kapasi, Jeffrey Schulz, Michael H. M. Chu, Caroline Ssu-Min Chen, Chiakang Sung
  • Patent number: 8930641
    Abstract: An integrated circuit may have a memory controller that interfaces between master processing modules and system memory. A scheduling module may be used to handle memory access requests received from multiple master modules. The scheduling module may arrange the received memory access requests in an order for fulfillment with system memory. A bypass module may be used to provide a low latency bypass path that allows memory access requests to bypass the scheduling module. The bypass module may include an eligibility detection module that identifies memory access requests eligible for scheduler bypassing, a port selection module that provides a low latency bypass path for the eligible memory access requests, multiplexing circuitry that selects between memory access requests provided from the low latency bypass path and from the output of the scheduling module, and a masking module that prevents redundant fulfillment of memory access requests.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 6, 2015
    Assignee: Altera Corporation
    Inventors: Ravish Kapasi, Jeffrey Schulz, Ching-Chi Chang, Caroline Ssu-Min Chen
  • Publication number: 20120311277
    Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 6, 2012
    Inventors: Michael H.M. Chu, Jeffrey Schulz, Chiakang Sung, Ravish Kapasi
  • Patent number: 7352751
    Abstract: An apparatus for transferring data in a telecommunications network. The apparatus includes a memory in which a packet memory length is stored. The apparatus includes a mechanism for determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network. The apparatus includes a mechanism for sending the packet having the link length to the network. A method for transferring data in a telecommunications network. The method includes the steps of storing in a memory a memory length of a packet. There is the step of determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network There is the step of sending the packet having the link length to the network.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: April 1, 2008
    Assignee: Ericsson AB
    Inventors: Veeranarayana A. Reddy, Joseph A. Hook, Jeremy William Horner, Jeffrey Schulz
  • Publication number: 20050041668
    Abstract: An apparatus for transferring data in a telecommunications network. The apparatus includes a memory in which a packet memory length is stored. The apparatus includes a mechanism for determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network. The apparatus includes a mechanism for sending the packet having the link length to the network. A method for transferring data in a telecommunications network. The method includes the steps of storing in a memory a memory length of a packet. There is the step of determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network There is the step of sending the packet having the link length to the network.
    Type: Application
    Filed: August 18, 2003
    Publication date: February 24, 2005
    Inventors: Veeranarayana Reddy, Joseph Hook, Jeremy Horner, Jeffrey Schulz