Abstract: A system includes a programmable logic fabric core of an integrated circuit device and an IO interface communicatively coupled to the programmable logic fabric core. The IO interface includes multiple IO banks to implement a memory channel. Each IO bank includes a memory controller to control memory accesses of a memory device over the memory channel and multiple physical layer and IOs circuits to provide connections between the memory controller and the memory device. The respective memory controller may receive only a portion of data to be sent over the memory channel or multiple memory controllers may each receive all data to be sent over the memory channel.

Abstract: A memory interface circuit includes first and second memory controller circuits that asynchronously receive requests for memory accesses to first and second storage circuits. The memory interface circuit also includes first and second clock gate circuits that disable and then reenable first and second clock signals in response to a clock enable signal. The first and the second memory controller circuits perform the memory accesses to the first and the second storage circuits synchronously in response to the first and the second clock signals that have been reenabled by the first and the second clock gate circuits.

Abstract: Systems or methods of the present disclosure may provide a programmable logic fabric and a memory controller communicatively coupled to the programmable logic fabric. The systems or methods also include a physical layer and IO circuit coupled to the programmable logic fabric via the memory controller and a FIFO to receive read data from a memory device coupled to the physical layer and IO circuit. Furthermore, the FIFO is closer to the memory controller than to the physical layer and IO circuit.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

Abstract: A convertible chassis system for receiving a plurality of storage drives includes a chassis that includes a plurality of bays for receiving the storage drives. The convertible chassis also includes a reversible key that is removably affixed to the chassis body in either a first orientation or a second orientation. Each orientation provides a different key guide within the plurality of bays that either allows the storage drives to be received into or rejected from the bays of the chassis.

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

Abstract: A convertible chassis system for receiving a plurality of storage drives includes a chassis that includes a plurality of bays for receiving the storage drives. The convertible chassis also includes a reversible key that is removably affixed to the chassis body in either a first orientation or a second orientation. Each orientation provides a different key guide within the plurality of bays that either allows the storage drives to be received into or rejected from the bays of the chassis.

Abstract: An example adapter assembly may comprise an adapter cage to removably mount to a riser board of a computer system. Further, the example adapter assembly may comprise an adapter board disposed on the adapter cage, wherein the adapter cage is to receive multiple computer components, and the adapter board is to engage with the multiple computer components.

Abstract: A server chassis installable in a server rack may include a lower compartment, an upper compartment, and an interconnector. The lower compartment may have a front end defining a front opening configured to allow for the passage of a server therethrough. The upper compartment may define a top opening substantially orthogonal to the front opening and may be configured to allow for the passage of a plurality of storage cartridges therethrough. The interconnector may have a first set of connectors communicatively coupled with a second set of connectors. The first set of connectors may be configured to mate with the server, and the second set of connectors may be configured to mate with the storage cartridges, such that the interconnector allows for the removal of the server without the removal of the storage cartridges.

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

Abstract: Input-output (IO) circuitry for optimizing power management on an integrated circuit is disclosed. The IO circuitry includes monitoring circuitry and a multiplexer circuit that is controlled by the monitoring circuitry. The monitoring circuitry determines whether majority of the bits of an IO signal are transitioning from a first logical state to a second logical state. When a number of bit transitions of the IO signal exceeds a predetermined bit transition threshold, the monitoring circuitry may send a monitoring circuitry output to the multiplexer circuit to selectively couple an output signal to either the IO signal or an inverted IO signal. The IO circuitry further includes an additional multiplexer that receives the monitoring circuitry output and a clock signal. The additional multiplexer selects an additional output signal from the monitoring circuitry output and the clock signal based on a control signal that indicates a power-savings operation.

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

Abstract: An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.

Abstract: Techniques and mechanisms handle transactions between various components of a memory controller. For example, a memory controller may include a component implemented in configurable logic and another component implemented in hard logic.

Abstract: A method and system for operating a multi-port memory system are disclosed. A memory controller may service read requests by accessing requested data from an external memory and communicating it to the requesting memory ports for access by devices coupled to the memory ports. A shared memory of the memory controller may be used to temporarily store data if a buffer associated with a requesting device is full. To reduce the ability for a slower memory port to occupy the shared memory and cause faster memory ports to be underserviced, the memory controller may advantageously regulate or limit issuance of read requests by memory ports operating at slower clock frequencies. The memory ports may be regulated independently of one another based on at least one respective attribute of each memory port, at least one attribute of the external memory, etc.

Abstract: A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.

Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have predetermined bit widths. To provide the memory controller with adjustable port widths, a mapping interface may be provided that interfaces between master processing modules and the memory controller. The mapping interface may allocate port resources such as read data ports and write data ports of the memory controller to each master processing module. The mapping interface may assign a desirable number of read data ports and write data ports to each master to accommodate the requirements of that master. The mapping interface may assign a command port to each master that receives memory access requests from that master. The mapping interface may convey write acknowledgements in response to fulfilling write access requests.

Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.