Abstract: A system and method providing timing alignment of a data mask (DM) signal with respect to a data strobe (DQS) signal for memory devices not designed for adjusting such alignment is provided. Alignment between data signals (DQ) and a DQS signal is first achieved during a first write training procedure where a data delay value is optimized for one of the DQS or DQ signals. Subsequently, using the optimum delay value from the first write training procedure, a second write training procedure is initiated. In the second write training procedure, timing alignment between the DM signal and the DQ signals is achieved by determining an optimal delay value of the DM signal relative to the DQS signal.

Abstract: A chip select signal is trained where the chip select signal is delayed to centrally align its pulses with a positive edge of a memory device's clock cycle. Over repeated iterations, the memory device stops its clock for an interval and a delayed pulse of the chip select signal is generated. The pulse delay is incrementally changed with each iteration. When the delay results in the trailing edge of the delayed pulse aligning with the positive edge of the last cycle before the stoppage interval, the memory device captures the contents of a computer bus, thus detecting a trailing edge delay value. When the delay results in the leading edge of the delayed pulse aligning with the positive edge of the last cycle, the device no longer captures the contents, thus detecting a leading edge delay value. A value between these values is then set as the optimal delay.