Patents by Inventor Jeffrey Shabel

Jeffrey Shabel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11803472
    Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 31, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Girish Bhat, Subbarao Palacharla, Jeffrey Shabel, Isaac Berk, Kedar Bhole, Vipul Gandhi, George Patsilaras, Sparsh Singhai
  • Publication number: 20230029696
    Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Girish Bhat, Subbarao Palacharla, Jeffrey Shabel, Isaac Berk, Kedar Bhole, Vipul Gandhi, George Patsilaras, Sparsh Singhai
  • Patent number: 11256894
    Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Wesley James Holland, Rashmi Kulkarni, Ling Feng Huang, Huang Huang, Jeffrey Shabel, Chih-Chi Cheng, Satish Anand, Songhe Cai, Simon Peter William Booth, Bohuslav Rychlik
  • Publication number: 20210200679
    Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 1, 2021
    Inventors: Andrew Edmund TURNER, George PATSILARAS, Bohuslav RYCHLIK, Wesley James HOLLAND, Jeffrey SHABEL, Simon Peter William BOOTH
  • Publication number: 20210174047
    Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Inventors: Wesley James HOLLAND, Rashmi KULKARNI, Ling Feng HUANG, Huang HUANG, Jeffrey SHABEL, Chih-Chi CHENG, Satish ANAND, Songhe CAI, Simon Peter William BOOTH, Bohuslav RYCHLIK
  • Patent number: 11016898
    Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 25, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Edmund Turner, George Patsilaras, Bohuslav Rychlik, Wesley James Holland, Jeffrey Shabel, Simon Peter William Booth
  • Publication number: 20210049099
    Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: ANDREW EDMUND TURNER, George PATSILARAS, Bohuslav RYCHLIK, Wesley James HOLLAND, Jeffrey SHABEL, Simon Peter William BOOTH
  • Patent number: 10747671
    Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: August 18, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Wesley James Holland, Bohuslav Rychlik, Andrew Edmund Turner, George Patsilaras, Jeffrey Shabel, Simon Peter William Booth
  • Publication number: 20200250101
    Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: GEORGE PATSILARAS, Wesley James Holland, Bohuslav Rychlik, Andrew Edmund Turner, Jeffrey Shabel, Simon Peter William Booth, Simo Petteri Kangaslampi, Christopher Koob, Wisnu Wurjantara, David Hansen, Ron Lieberman, Daniel Palermo, Colin Sharp, Hao Liu
  • Publication number: 20200250097
    Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: WESLEY JAMES HOLLAND, Bohuslav Rychlik, Andrew Edmund Turner, George Patsilaras, Jeffrey Shabel, Simon Peter William Booth
  • Publication number: 20190012271
    Abstract: One feature pertains to an apparatus that includes a memory circuit, a system memory-management unit (SMMU), and a processing circuit. The memory circuit stores an executable program associated with a client. The SMMU enforces memory access control policies for the memory circuit, and includes a plurality of micro-translation lookaside buffers (micro-TLBs), macro-TLB, and a page walker circuit. The plurality of micro-TLBs include a first micro-TLB that enforces memory access control policies for the client. The processing circuit loads memory address translations associated with the executable program into the first micro-TLB, and initiates isolation mode for the first micro-TLB causing communications between the first micro-TLB and the macro-TLB and between the first micro-TLB and the page walker circuit to be severed. The first micro-TLB continues to enforce memory access control policies for the client while in isolation mode.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 10, 2019
    Inventors: Christophe AVOINNE, Samar ASBE, Thomas ZENG, Jean-Louis TARDIEUX, Jeffrey SHABEL, Azzedine TOUZNI
  • Patent number: 10061644
    Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Nhon Quach, Mainak Biswas, Pranjal Bhuyan, Jeffrey Shabel, Robert Hardacker, Rahul Gulati, Mattheus Heddes
  • Publication number: 20170123897
    Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.
    Type: Application
    Filed: January 12, 2016
    Publication date: May 4, 2017
    Inventors: Nhon Quach, Mainak Biswas, Pranjal Bhuyan, Jeffrey Shabel, Robert Hardacker, Rahul Gulati, Mattheus Heddes