Patents by Inventor Jeffrey Sherry
Jeffrey Sherry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11467183Abstract: A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top—in or bottom—in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.Type: GrantFiled: October 5, 2020Date of Patent: October 11, 2022Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Joël Erdman
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Patent number: 11360117Abstract: A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave port 20 and a load board via a waveguide structure. The waveguide includes a wave insert 42, a waveguide adapter 24 and a conductive compliant member 40 which maintains bias between the adapter 24 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projection 64 which is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.Type: GrantFiled: June 24, 2020Date of Patent: June 14, 2022Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Cory Kostuchowski
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Patent number: 11307232Abstract: A structure and method for providing a housing which includes a high frequency (HF or RF) connection between a device under test (DUT) having a waveguide 22. The waveguide includes a wave insert 22, and a conductive compliant member 40 which maintains bias between the adapter/insert 22 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT waveport. A passage 50 provides an RF connection between the RF port 62 on the DUT and a RF wave guide horn 54. A plurality of transmitting horns 54 can be arranged to transmit to a single receiving horn 154 so that fewer receivers are required to test multiple DUTs in sequence.Type: GrantFiled: February 20, 2020Date of Patent: April 19, 2022Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Cory Kostuchowski
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Patent number: 11293968Abstract: A testing system and method for testing integrated circuits with radio frequency (RF) antennas is disclosed. The system includes an alignment plate for receiving a device under test (DUT) having an RF transmitting antenna, an enclosure surrounding but separated from the transmitting antenna, a receiving antenna in a telescopic enclosure, and a conversion circuit connected to the receiving antenna. The conversion circuit is configured to convert an RF output from the DUT to a direct current (DC) voltage. The DC voltage is used as a proxy for the RF output to test the DUT. When testing chips with RF ports, the chip or ports are surrounded by the enclosure which is non-radio reflective and includes antennas for receiving RF outputs disbursed around the enclosure, or a single antenna. If multiple receiving antennas are used, sequential testing can also detect directional transmission patterns to confirm that the direction is correctly calibrated.Type: GrantFiled: May 12, 2020Date of Patent: April 5, 2022Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventor: Jeffrey Sherry
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Patent number: 11209458Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are protected against damage from balls on a DUT by a protective ball guide which includes recesses for receiving part of the ball but prevents the ball from driving the pins beyond a limited range. The ball guide provides fine alignment horizontally and vertically enabling stable electrical performance.Type: GrantFiled: July 27, 2020Date of Patent: December 28, 2021Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventors: John Nelson, Ranauld Perez, Jeffrey Sherry, Michael Andres, David Johnson
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Patent number: 11183783Abstract: A test socket (14) for a testing an integrated circuit (12) with controlled impedance while maintaining the structural integrity of the test pins (20). The pin (20) can have a sidewall with a thick portion 32 and a thinner portion (30) along the length of the pin. The pin can have projections (42) which provide a standoff from the slot (40). The sidewalls themselves can have projections or lands (60, 61) which extend into the slot and provide stability for the pin (20).Type: GrantFiled: June 15, 2020Date of Patent: November 23, 2021Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Michael Andres
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Publication number: 20210356511Abstract: A testing system and method for testing integrated circuits with radio frequency (RF) antennas is disclosed. The system includes an alignment plate for receiving a device under test (DUT) having an RF transmitting antenna, an enclosure surrounding but separated from the transmitting antenna, a receiving antenna in a telescopic enclosure, and a conversion circuit connected to the receiving antenna. The conversion circuit is configured to convert an RF output from the DUT to a direct current (DC) voltage. The DC voltage is used as a proxy for the RF output to test the DUT. When testing chips with RF ports, the chip or ports are surrounded by the enclosure which is non-radio reflective and includes antennas for receiving RF outputs disbursed around the enclosure, or a single antenna. If multiple receiving antennas are used, sequential testing can also detect directional transmission patterns to confirm that the direction is correctly calibrated.Type: ApplicationFiled: May 12, 2020Publication date: November 18, 2021Inventor: Jeffrey Sherry
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Patent number: 11002760Abstract: A system and method for reducing inductance and capacitance and shielding signals in an integrated circuit test for devices under test (DUT) is disclosed. Inductance and capacitance are reduced in two ways. First, by recessing the contact pin housing 22 directly into the load board 20 thereby eliminating much of distance between the load board and DUT. Second, surrounding the slot/well 50 in which each RF contact pin resides in the housing with a ground isolation cage 46,46a, 48, 47 of electrically conductive strips or rings at the top and bottom of the housing adjacent the slot with connecting vias thereby creating an isolation cage against RF cross talk transmission and further lowering inductance and capacitance.Type: GrantFiled: February 6, 2018Date of Patent: May 11, 2021Inventors: Jeffrey Sherry, Dennis Wagner
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Patent number: 10928423Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.Type: GrantFiled: September 4, 2018Date of Patent: February 23, 2021Assignee: Johnstech International CorporationInventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
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Publication number: 20210018533Abstract: A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top—in or bottom—in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Jeffrey Sherry, Joel Erdman
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Publication number: 20200363451Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are protected against damage from balls on a DUT by a protective ball guide which includes recesses for receiving part of the ball but prevents the ball from driving the pins beyond a limited range. The ball guide provides fine alignment horizontally and vertically enabling stable electrical performance.Type: ApplicationFiled: July 27, 2020Publication date: November 19, 2020Inventors: John Nelson, Ranauld Perez, Jeffrey Sherry, Michael Andres, David Johnson
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Patent number: 10794933Abstract: A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top—in or bottom—in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.Type: GrantFiled: June 13, 2017Date of Patent: October 6, 2020Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Joel Erdman
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Publication number: 20200313322Abstract: A test socket (14) for a testing an integrated circuit (12) with controlled impedance while maintaining the structural integrity of the test pins (20). The pin (20) can have a sidewall with a thick portion 32 and a thinner portion (30) along the length of the pin. The pin can have projections (42) which provide a standoff from the slot (40). The sidewalls themselves can have projections or lands (60, 61) which extend into the slot and provide stability for the pin (20).Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Jeffrey Sherry, Michael Andres
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Patent number: 10725069Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are protected against damage from balls on a DUT by a protective ball guide which includes recesses for receiving part of the ball but prevents the ball from driving the pins beyond a limited range. The ball guide provides fine alignment horizontally and vertically enabling stable electrical performance.Type: GrantFiled: September 18, 2018Date of Patent: July 28, 2020Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventors: John Nelson, Ranauld Perez, Jeffrey Sherry, Michael Andres, David Johnson
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Patent number: 10698000Abstract: A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave port 20 and a load board via a waveguide structure. The waveguide includes a wave insert 42, a waveguide adapter 24 and a conductive compliant member 40 which maintains bias between the adapter 24 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projection 64 which is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.Type: GrantFiled: April 24, 2019Date of Patent: June 30, 2020Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Cory Kostuchowski
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Patent number: 10686269Abstract: A test socket (14) for a testing an integrated circuit (12) with controlled impedance while maintaining the structural integrity of the test pins (20). The pin (20) can have a sidewall with a thick portion 32 and a thinner portion (30) along the length of the pin. The pin can have projections (42) which provide a standoff from the slot (40). The sidewalls themselves can have projections or lands (60, 61) which extend into the slot and provide stability for the pin (20).Type: GrantFiled: September 25, 2018Date of Patent: June 16, 2020Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventors: Jeffrey Sherry, Michael Andres
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Patent number: 10274515Abstract: A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave port 20 and a load board via a waveguide structure. The waveguide includes a wave insert 42, a waveguide adapter 24 and a conductive compliant member 40 which maintains bias between the adapter 24 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projection 64 which is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.Type: GrantFiled: August 4, 2016Date of Patent: April 30, 2019Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Cory Kostuchowski
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Publication number: 20190097333Abstract: A test socket (14) for a testing an integrated circuit (12) with controlled impedance while maintaining the structural integrity of the test pins (20). The pin (20) can have a sidewall with a thick portion 32 and a thinner portion (30) along the length of the pin. The pin can have projections (42) which provide a standoff from the slot (40). The sidewalls themselves can have projections or lands (60, 61) which extend into the slot and provide stability for the pin (20).Type: ApplicationFiled: September 25, 2018Publication date: March 28, 2019Inventors: Jeffrey Sherry, Michael Andres
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Publication number: 20190004093Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.Type: ApplicationFiled: September 4, 2018Publication date: January 3, 2019Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
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Patent number: 10067164Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.Type: GrantFiled: August 24, 2016Date of Patent: September 4, 2018Assignee: Johnstech International CorporationInventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult