Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n?1) different reference values, and having N sets of (n?1) output terminals for outputting N sets of (n?1) output signals indicating whether the value of the multi-level signal is below or above the (n?1) reference values. The circuitry also includes N sets of (n?1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n?1) sample-and-hold circuits for generating at least one binary signal having a period N*T.

Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n?1) different reference values, and having N sets of (n?1) output terminals for outputting N sets of (n?1) output signals indicating whether the value of the multi-level signal is below or above the (n?1) reference values. The circuitry also includes N sets of (n?1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n?1) sample-and-hold circuits for generating at least one binary signal having a period N*T.

Abstract: A novel 100+ Gbit/s opto-electronic receiver uses hybrid integration of a photodiode and a demultiplexer. The photodiode converts a high speed optical data stream to an electrical data stream that is input to an electronic demultiplexer. The photodiode and the demultiplexer are connected together by a novel planar microwave transmission structure.

Abstract: A novel 100+ Gbit/s opto-electronic receiver uses hybrid integration of a photodiode and a demultiplexer. The photodiode converts a high speed optical data stream to an electrical data stream that is input to an electronic demultiplexer. The photodiode and the demultiplexer are connected together by a novel planar microwave transmission structure.

Abstract: An optoelectronic integrated circuit (OEIC) having an optical core coupled to first and second interface circuits. The first interface circuit is adapted to convert an electrical input signal into an optical signal; the optical core is adapted to process the optical signal in the optical domain; and the second interface circuit is adapted to convert the processed optical signal into an electrical output signal. In one embodiment, an OEIC of the invention is fabricated using a single wafer, has only electrical inputs/outputs, does not have any external optical interfaces, and is not adapted to receive any external optical signals. Advantageously, due to the signal processing being in the optical domain, a circuit of the invention carries out its functionality, with little or no performance degradation, over a relatively wide frequency range. In addition, this circuit has a relatively small size and can be relatively inexpensive.

Abstract: A (binary) signal is transmitted through an electrical backplane, and the received signal is interpreted as a duobinary signal. In order to ensure that the received signal can be properly interpreted as a duobinary signal, the data signal is preferably filtered prior to being interpreted. The filter is preferably designed such that the combination of filter and the backplane approximates a binary-to-duobinary converter. In one embodiment, an (FIR-based) equalizing filter is applied to the data signal prior to transmission to emphasize the high-frequency components and flatten the group delay of the backplane. The resulting, received duobinary signal is converted into a binary signal by (1) splitting the duobinary signal, (2) applying each copy to a suitably thresholded comparator, and (3) applying the comparator outputs to a suitable (e.g., XOR) logic gate. The transmission system enables high-speed data (e.g., greater than 10 Gb/s) to be transmitted over relatively inexpensive electrical backplanes.

Abstract: A technique for performance-monitoring of a standard SONET signal involves first converting the optical signal to an electrical signal, removing in the framing signal time slot the framing signal for leaving only the framing signal noise in such time slot, and separating the framing signal noise from the data signal for viewing as a measure of the quality of the SONET signal.

Abstract: In one embodiment, a duobinary-to-binary signal converter includes a pair of comparators coupled to a logic gate. Each comparator receives a copy of a duobinary-encoded analog signal applied to the converter and is designed to generate a binary output based on the comparison of the magnitude of the received signal with a corresponding threshold voltage. The outputs of the comparators are fed into the logic gate, which generates a binary sequence corresponding to the duobinary-encoded signal. A representative converter of the invention can perform relatively well at bit rates as high as about 40 Gb/s and can be conveniently incorporated into an appropriate integrated device (e.g., an ASIC) for a data transmission system employing duobinary signaling.