Abstract: A mask-programmable read only memory bit cell (16) has a pair of conductive elements for each conductive layer in the integrated device but the last layer (30 and 34, 38 and 42, 46 and 50) and single conductive element in the last layer (54). The first and second elements in the first pair of elements receive a first and a second voltage supply (V.sub.DD and V.sub.GND), respectively. The single element outputs a voltage corresponding to the logic state stored by the bit cell. A plurality of pairs of conductive vias couple particular ones of the elements in each layer to particular ones of the elements in adjacent layers. The logic state stored by the bit cell may be reversed by reversing the connection of any one pair of elements and its associated vias. This makes the bit cell suitable for use in a processor version register.