Abstract: A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.

Abstract: Methods and systems are provided by which a computer system, and in particular, a lockstep fault-tolerant computer system, may be split into a plurality of independently operational subsystems. Each subsystem may be examined, managed or upgraded by an administrator while the overall computer system continues to service end-users. Finally, the separate subsystems may be merged in an efficient fashion and fault-tolerant operation will resume upon the combined system.

Abstract: A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.

Abstract: A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.

Abstract: A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.

Abstract: Methods and systems are provided by which a computer system, and in particular, a lockstep fault-tolerant computer system, may be split into a plurality of independently operational subsystems. Each subsystem may be examined, managed or upgraded by an administrator while the overall computer system continues to service end-users. Finally, the separate subsystems may be merged in an efficient fashion and fault-tolerant operation will resume upon the combined system.

Abstract: Systems and methods are disclosed for facilitating synchronous communications over an asynchronous communications link. Specifically, embodiments of the claimed invention provide systems and methods for transmitting high-speed signals while maintaining lock-step determinism using remote clock phase adjustments. Embodiments of the claimed invention also provide systems and methods for maintaining determinism through the use of synchronized time slice counters within the various components.

Abstract: Systems and methods are disclosed for facilitating synchronous communications over an asynchronous communications link. Specifically, embodiments of the present invention provide systems and methods for transmitting high-speed signals while maintaining lock-step determinism using remote clock phase adjustments. Embodiments of the present invention also provide systems and methods for maintaining determinism through the use of synchronized time slice counters within the various components.

Abstract: The present invention relates to a method and system for transferring portions of a memory block. A first data mover is configured with a first start address corresponding to a first portion of a source memory block. A second data mover is configured with a second start address corresponding to a second portion of the source memory block sized differently from the first portion. The first portion of the source memory block is transferred by the first data mover and the second portion of the source memory block is transferred by the second data mover.

Abstract: A method and apparatus for maintaining clock phase alignment among system modules of a fault-tolerant computing system. In one embodiment, a low-frequency system reference clock signal is distributed to all system modules where it is multiplied to generate higher-frequency local clock signals. All local clock signals are then synchronized to the rising edge of the reference clock signal and the first rising edge in relation to a timing event is also identified.

Abstract: A method and apparatus for controlling processor clock rates of a synchronous multi-processor system in response to an environmental condition of a processor. In one embodiment, a processor-reported an environmental condition is stored in a register and all processors are interrupted simultaneously. Upon interrupt, each processor reads the contents of the register and responds by adjusting its local clock rate synchronously with the other processors. In another embodiment, the processor's environmental status is polled by software control. Upon notification of an environmental condition, the software control notifies each processor to adjust its local clock rate synchronously with the other processors.

Abstract: The present invention relates to a method and system for transferring portions of a memory block. A first data mover is configured with a first start address corresponding to a first portion of a source memory block. A second data mover is configured with a second start address corresponding to a second portion of the source memory block sized differently from the first portion. The first portion of the source memory block is transferred by the first data mover and the second portion of the source memory block is transferred by the second data mover.