Patents by Inventor Jeffrey Strait

Jeffrey Strait has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120093252
    Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 19, 2012
    Applicant: Metanoia Technologies, Inc.
    Inventor: Jeffrey Strait
  • Publication number: 20060093023
    Abstract: A multicarrier transceiver is disclosed that includes a digital signal processor with a plurality of memory locations, a direct memory, an encoder module coupled to receive data from the FIFO buffers, a decoder module coupled to receive data from the FIFO buffers, a Fourier transform module configured to perform an inverse Fast Fourier transform for transmit operations and to perform Fast Fourier transform (FFT) operations for receive operations, a plurality of distributed modules including the encoder module, the decoder module and the Fourier transform module, each module configured with a memory port, each memory port coupled to a peripheral bus and the DMA bus, a plurality of memory ports coupled to each of the distributed modules, the plurality of memory ports coupled to a peripheral bus, and a plurality of point-to-point buses coupled to each of the distributed modules, the point-to-point bus configured to enable data flow and testing and provide a bypass capability for each of the distributed modules.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Terry Brown, Christopher Hansen, Jeffrey Strait, Ravi Mantri, Felician Bors