Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.

Abstract: Circuits, systems, and methods for dynamically controlling a power supply configuration in response to load requirements from a digital circuit are disclosed. To increase efficiency, the power supply is configurable to be switched into a lower capacity mode. To prevent the digital circuit from demanding capacity beyond the lower capacity mode of the power supply before the power supply can be switched into a higher capacity mode, at least one hardware interlock is employed. The hardware interlock(s) governs the power demand of the digital circuit from extending beyond the lower capacity mode of the power supply. If it is detected that the hardware interlock(s) limits power demand in the digital circuit beyond a power demand threshold, the power supply can be switched to the higher capacity mode. The hardware interlock(s) can then be disabled. In this manner, the power supply can dynamically provide increased capacity as demanded by the dynamic performance of the digital circuit.

Abstract: Circuits, systems, and methods for dynamically controlling a power supply configuration in response to load requirements from a digital circuit are disclosed. To increase efficiency, the power supply is configurable to be switched into a lower capacity mode. To prevent the digital circuit from demanding capacity beyond the lower capacity mode of the power supply before the power supply can be switched into a higher capacity mode, at least one hardware interlock is employed. The hardware interlock(s) governs the power demand of the digital circuit from extending beyond the lower capacity mode of the power supply. If it is detected that the hardware interlock(s) limits power demand in the digital circuit beyond a power demand threshold, the power supply can be switched to the higher capacity mode. The hardware interlock(s) can then be disabled. In this manner, the power supply can dynamically provide increased capacity as demanded by the dynamic performance of the digital circuit.

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.

Abstract: A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

Abstract: In a multi-threading microprocessor, a queue for a scarce resource such as a multiplier alternates on a fine-grained basis between instructions in various threads. When a long-latency instruction is discovered in a thread, the instructions in that thread that depend on the latency are flushed out of the thread until the latency is resolved, with the instructions in other threads filling empty slots from the thread waiting for the long-latency instruction and continuing to execute without being delayed by having to wait for the long-latency instruction.

Abstract: A pointer (86) has generate circuitry (90), propagate circuitry (90), carry circuitry (90) and detector circuitry (92). The pointer is for use with a buffer to designate one of a plurality of entries of the buffer. The generate circuitry receives a first and a second data word and generates a plurality of local generate functions. One bit of the first data word, second data word, and one of the local generate functions each corresponds to one of the entries of the buffer. Each data bit of the first data word is representative of the eligibility of the pointer to designate an entry. The second data word is representative of the pointer location at a previous time. The propagate circuitry receives the first and second data words and generates a plurality of local propagate functions. Each local propagate function corresponds to one of the entries of the buffer. The carry circuitry is coupled to the generate circuitry and to the propagate circuitry and generates a plurality of carry bits.

Abstract: A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A.sub.1, A.sub.2, A.sub.3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.