Patents by Inventor Jeffrey Techau

Jeffrey Techau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for forcing hardware errors via scan
    Patent number: 5452309
    Abstract: An apparatus and method for forcing stuck-at and transient errors at sequential and combinational logic and signal lines in a large scale data processing system. Error forcing is achieved by including a scan-in gate with error input and address lines for each scan point to be tested. A fault signal of adjustable duration is generated and combined in a unique fashion to an existing scan-in signal to permit either stuck-at or transient errors to be forced.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: September 19, 1995
    Assignee: Amdahl Corporation
    Inventors: David T. Ino, Patricia A. Simonson, Jeffrey A. Techau, Richard H. Larson
  • Scannable system with addressable scan reset groups
    Patent number: 5271019
    Abstract: A set of scan latches is partitioned into unique groups where each group is addressable by a group initializing circuit. The group initializing circuit initializes all the latches of an addressed group to a predefined state thereby quickly loading a test vector into the addressed group of scan latches while leaving other latches undisturbed.
    Type: Grant
    Filed: March 15, 1991
    Date of Patent: December 14, 1993
    Assignee: Amdahl Corporation
    Inventors: Robert Edwards, Jeffrey Techau, Rita Rudolph