Abstract: An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element having more than one impermissible operation. A code generator accepts a clock signal and generates a test code in response to it. A decoder accepts the test code and generates at least two output lines to disable the impermissible operations during the test. When the decoder is in a decode disabled condition, the output lines reflect a value that permit all possible memory operations.

Abstract: A memory array test system and method provides for testing a memory array in a manufactured chip. In accordance with one aspect of the invention, a system includes memory test input logic that acquires test data via a data port, a memory test enable logic and a memory test output logic. In accordance with another aspect of the invention, a method acquires test data via a data port, writes the test data to a memory address in the memory array, and reads output data from the memory address in the memory array. Then, the method compares the test data and the output data to determine if the memory address in the memory array passes a test.

Abstract: Generating a data path macro cell based upon a text format template comprising variables. The system provides for creating a text format template by generating a text format representation of a data path macro cell based upon data representing a graphical layout of the data path macro cell. Variables are substituted for constants. Variables are changed to values associated with a macro cell having desired characteristics to create a text format file representative of a desired macro cell. Graphical data representing the layout of a macro cell is generated based upon the text format file.

Abstract: At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

Abstract: Generating a data path macro cell based upon a text format template comprising variables. The system provides for creating a text format template by generating a text format representation of a data path macro cell based upon data representing a graphical layout of the data path macro cell. Variables are substituted for constants. Variables are changed to values associated with a macro cell having desired characteristics to create a text format file representative of a desired macro cell. Graphical data representing the layout of a macro cell is generated based upon the text format file.

Abstract: A memory array test system and method provides for testing a memory array in a manufactured chip. In accordance with one aspect of the invention, a system includes memory test input logic that acquires test data via a data port, a memory test enable logic and a memory test output logic. In accordance with another aspect of the invention, a method acquires test data via a data port, writes the test data to a memory address in the memory array, and reads output data from the memory address in the memory array. Then, the method compares the test data and the output data to determine if the memory address in the memory array passes a test.

Abstract: At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

Abstract: An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element 104 having one or more impermissible operations. A code generator 401 accepts a clock signal 218 and generates a test code in response to it. A decoder 402 accepts the test code and generates at least two output lines 318, 319, 320, 321 where when in a decode enabled condition, the output lines 318, 319, 320, 321 are responsive to the test code and reflect a value that is combined with respective memory access lines comprising first and second write address outputs 309, 310 and first and second read address outputs 311, 312 as well as enable bits from first and second write enable registers 210, 211 and first and second read enable registers 214, 215 to disable the one or more impermissible operations. When the decoder 402 is in a decode disabled condition, the output lines 318, 319, 320, 321 reflect a value that when combined with the respective memory access lines enables all possible memory operations.