Patents by Inventor Jeffrey W. Einarson

Jeffrey W. Einarson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6704781
    Abstract: A method of providing caching services to a server in a network. An offer of caching services is sent from a caching device to a server. The server receives the offer from the caching device and determines whether to accept the offer of caching services from the caching device. An authorization is sent from the server to the caching device when, as a result of the determining, the server determines to accept the offer of caching services. The caching device stores content from the server after the sending of the authorization from the server to the caching device.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: March 9, 2004
    Assignee: Intel Corporation
    Inventors: Jeffrey W. Einarson, Narayan R. Manepally, Holland J. Wood
  • Patent number: 5062036
    Abstract: Instruction prefetching apparatus particularly adapted to executing an EXECUTE instruction specifiying a single subject instruction. The apparatus includes a first and second separately-controllable instruction syllable register and control apparatus. Under control of the control apparatus, the first instruction syllable register receives only the first syllable of the prefetched instruction; the second instruction syllable register receives all other syllables. The instruction syllable registers may be loaded either directly from memory or from a data register internal to the CPU. In the first case, the address of the instruction syllable to be prefetched is contained in a special instruction address register which is incremented each time an instruction syllable register is loaded. In the second case, the loading does not affect the value of the instruction address register.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: October 29, 1991
    Assignee: Wang Laboratories, Inc.
    Inventors: Arthur Barrow, Kin L. Cheung, Jeffrey W. Einarson, Shams A. Khan
  • Patent number: 4799187
    Abstract: Address generating apparatus for use in a computer system which includes a bus processor, a memory requiring 24-bit addresses, and a plurality of I/O processors, some of which generates 22-bit addresses and others of which generate 24-bit addresses on a system bus connecting them with the memory. The apparatus provides a 2-bit prefix to the address on the system bus when the address on the bus comes from a 22-bit device. The 22-bit devices are specified by a mask register and the prefixes by a set of prefix registers, one for each of the devices. When bus grant logic in the computer system determines which of the devices is to have control of the system bus, logic in the address generating apparatus determines from the mask register whether the device which is to receive control requires a prefix. If it does, the address generating apparatus outputs the device's prefix to the system bus's two most significant address lines at the same time as the device outputs a 22-bit address to the remaining address lines.
    Type: Grant
    Filed: July 30, 1987
    Date of Patent: January 17, 1989
    Assignee: Wang Laboratories, Inc.
    Inventors: Jeffrey W. Einarson, Kin-Ling Cheung
  • Patent number: 4685082
    Abstract: A simplified cache with automatic updating for use in a memory system. The cache and the main memory receive data from a common input, and when a memory write operation is performed on data stored at a memory location for which there is a corresponding cache location, the data is written simultaneously to the cache and to the main memory. Since a cache location coresponding to a memory location always contains a copy of the data at the memory location, there is no need for dirty bits or valid bits in the cache resisters and the associated logic in the cache control. The main memory used with the invention may receive data either from a CPU or from I/O devices, and the cache includes apparatus permitting the CPU to perform cache read operations while the main memory is receiving data from an I/O device.
    Type: Grant
    Filed: February 22, 1985
    Date of Patent: August 4, 1987
    Assignee: Wang Laboratories, Inc.
    Inventors: Kin L. Cheung, Jeffrey W. Einarson