Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer comprising amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-comprising layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-comprising layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-comprising layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract: A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack including one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the gate stack, the partial etching step being completed before any of the gate oxide layer is exposed. Sidewall spacers are formed on edge surfaces of the partially formed gate electrode. Source and drain regions are created by ion implantation using the partially etched gate electrode and the sidewall spacers as a mask. The sidewall spacers are removed and lightly doped drain regions are formed by ion implantation using the partially etched gate electrode as a mask.

Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer including amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-including layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-including layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-including layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract: A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

Abstract: An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covered by a titanium layer, a top surface covered by a titanium layer, and opposing side surfaces covered by discrete titanium layers. The encapsulation of the aluminum layer within the titanium layers substantially precludes void formation within the aluminum layer. The interconnect line also may be upon a contact plug that is in electrical communication with an active area in an underlying semiconductor substrate.

Abstract: A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack comprising one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the gate stack, the partial etching step being completed before any of the gate oxide layer is exposed. Sidewall spacers are formed on edge surfaces of the partially formed gate electrode. Source and drain regions are created by ion implantation using the partially etched gate electrode and the sidewall spacers as a mask. The sidewall spacers are removed and lightly doped drain regions are formed by ion implantation using the partially etched gate electrode as a mask.

Abstract: A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

Abstract: The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. Isolation structure height may also be used as a diffraction grating for stepper alignment.

Abstract: The invention encompasses a method of forming an insulative material along a conductive structure. A conductive structure is provided over a substrate, and an electrically insulative material is formed along at least a portion of the conductive structure. The electrically insulative material comprises at least one of SixOyNz and AlpOq, wherein p, q, x, y and z are greater than 0 and less than 10. A dopant barrier layer is formed over the electrically insulative material. BPSG is formed over the dopant barrier layer, and the dopant barrier layer prevents dopant migration from the BPSG to the electrically insulative material. The invention also encompasses transistor structures, and methods of forming transistor structures.

Abstract: Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.

Abstract: The invention encompasses a method of forming an insulative material along a conductive structure. A conductive structure is provided over a substrate, and an electrically insulative material is formed along at least a portion of the conductive structure. The electrically insulative material comprises at least one of SixOyNz and AlpOq, wherein p, q, x, y and z are greater than 0 and less than 10. A dopant barrier layer is formed over the electrically insulative material. BPSG is formed over the dopant barrier layer, and the dopant barrier layer prevents dopant migration from the BPSG to the electrically insulative material. The invention also encompasses transistor structures, and methods of forming transistor structures.

Abstract: Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.

Abstract: The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. Isolation structure height may also be used as a diffraction grating for stepper alignment.

Abstract: An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covered by a titanium layer, a top surface covered by a titanium layer, and opposing side surfaces covered by discrete titanium layers. The encapsulation of the aluminum layer within the titanium layers substantially precludes void formation within the aluminum layer. The interconnect line also may be upon a contact plug that is in electrical communication with an active area in an underlying semiconductor substrate.

Abstract: An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covered by a titanium layer, a top surface covered by a titanium layer, and opposing side surfaces covered by discrete titanium layers. The encapsulation of the aluminum layer within the titanium layers substantially precludes void formation within the aluminum layer. The interconnect line also may be upon a contact plug that is in electrical communication with an active area in an underlying semiconductor substrate.

Abstract: The invention encompasses a method of forming an insulative material along a conductive structure. A conductive structure is provided over a substrate, and an electrically insulative material is formed along at least a portion of the conductive structure. The electrically insulative material comprises at least one of SixOyNz and AlpOq, wherein p, q, x, y and z are greater than 0 and less than 10. A dopant barrier layer is formed over the electrically insulative material. BPSG is formed over the dopant barrier layer, and the dopant barrier layer prevents dopant migration from the BPSG to the electrically insulative material. The invention also encompasses transistor structures, and methods of forming transistor structures.

Abstract: A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

Abstract: The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. Isolation structure height may also be used as a diffraction grating for stepper alignment.

Abstract: The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. The height of the isolation structure can also be used as a diffraction grating for stepper alignment.

Abstract: An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covered by a titanium layer, a top surface covered by a titanium layer, and opposing side surfaces covered by discrete titanium layers. The encapsulation of the aluminum layer within the titanium layers substantially precludes void formation within the aluminum layer. The interconnect line also may be upon a contact plug that is in electrical communication with an active area in an underlying semiconductor substrate.