Patents by Inventor Jeffrey W. Janzen
Jeffrey W. Janzen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8559238Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.Type: GrantFiled: January 12, 2012Date of Patent: October 15, 2013Assignee: Round Rock Research, LLCInventor: Jeffrey W. Janzen
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Patent number: 8339888Abstract: A system with a memory device having programmable elements used to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device is incorporated into a system. Once the memory device is incorporated into a system, the programmable elements may be accessed by a processor such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for the memory device in the system.Type: GrantFiled: October 19, 2011Date of Patent: December 25, 2012Assignee: Round Rock Research, LLCInventors: Jeffrey W. Janzen, Scott Schaefer, Todd D. Farrell
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Publication number: 20120246434Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.Type: ApplicationFiled: June 5, 2012Publication date: September 27, 2012Inventors: Jeffrey W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
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Patent number: 7280410Abstract: A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.Type: GrantFiled: October 3, 2006Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventors: Jeffrey W. Janzen, Christopher Morzano
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Patent number: 7215579Abstract: A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.Type: GrantFiled: February 18, 2005Date of Patent: May 8, 2007Assignee: Micron Technology, Inc.Inventors: Jeffrey W. Janzen, Christopher Morzano
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Patent number: 7057967Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal.Type: GrantFiled: December 1, 2004Date of Patent: June 6, 2006Inventors: Brian Johnson, Brent Keeth, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin
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Patent number: 6931483Abstract: A method comprising reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device and ignoring said certain address bits before inputting at least one n-bit word into said memory array. The method may additionally comprise examining at least two of the least significant bits of a column address and wherein said reordering is responsive to said examining step. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0-CA2 identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0-CA2 being “don't care” bits assumed to be 000.Type: GrantFiled: April 26, 2004Date of Patent: August 16, 2005Assignee: Micron Technology, Inc.Inventor: Jeffrey W. Janzen
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Patent number: 6845433Abstract: A system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis is disclosed. A memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer. If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command.Type: GrantFiled: September 15, 2003Date of Patent: January 18, 2005Assignee: Micron Technology, Inc.Inventor: Jeffrey W. Janzen
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Patent number: 6842398Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal.Type: GrantFiled: November 7, 2003Date of Patent: January 11, 2005Assignee: Micron Technology, Inc.Inventors: Brian Johnson, Brent Keeth, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin
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Publication number: 20040080996Abstract: A system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis is disclosed. A memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer. If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command.Type: ApplicationFiled: September 15, 2003Publication date: April 29, 2004Inventor: Jeffrey W. Janzen
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Patent number: 6678205Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency.Type: GrantFiled: December 26, 2001Date of Patent: January 13, 2004Assignee: Micron Technology, Inc.Inventors: Brian Johnson, Brent Keeth, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin
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Patent number: 6647470Abstract: A system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis is disclosed. A memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer. If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command.Type: GrantFiled: August 21, 2000Date of Patent: November 11, 2003Assignee: Micron Technology, Inc.Inventor: Jeffrey W. Janzen
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Patent number: 6040983Abstract: In a surface mount assembly, an active integrated circuit device, such as, for example, a dynamic random access memory, typically has a lead finger attached to a solder pad of a printed wiring board. The surface mount assembly is significantly improved by configuring a passive component, such as a resistor or capacitor, such that it has metallic terminations on an upper and lower surface so that it may be positioned between the solder pad of the printed wiring board and the lead finger.Type: GrantFiled: March 13, 1998Date of Patent: March 21, 2000Assignee: Texas Instruments IncorporatedInventors: Daniel Baudouin, Ernest J. Russell, Jeffrey W. Janzen