Abstract: A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode.

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Abstract: A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. The speculative read request has a corresponding access address. The bus interface unit is configured to communicate with an external system interconnect. The cache includes a cache array and cache control circuitry. The cache control circuitry is configured to receive the discard signal from the instruction pipeline and, when the discard signal is asserted after the access address has been provided to the external system interconnect by the bus interface unit in response to a determination by the cache control circuitry that the access address missed in the cache array, selectively store the read information returned from the access address into the cache array.

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Abstract: A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. An entry at a branch target buffer corresponding to the branch instruction is selectively allocated based on a result of the comparing.

Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.

Abstract: A system includes a focal plane array (FPA), support structure, optical assembly, flexing structure, and drive actuator. The FPA includes multiple pixels. The FPA captures an image as image data during an integration time interval. The optical assembly is fixed to the support structure and forms an image of a scene at the FPA. The flexing structure is mechanically coupled to both the support structure and the FPA, and allows the FPA to move relative to the support structure. The actuator is mechanically coupled to the FPA, and drives the FPA to move relative to the support structure. Some FPA have all readout elements arranged in a first regular grid with constant spacing, while some detector elements are on that grid and other detector elements are on a different grid offset by less than the constant spacing to provide sub-pixel resolution.

Abstract: A processor is configured to execute instructions of a first thread and a second thread. A first return stack corresponds to the first thread, and a second return stack to the second thread. Control circuitry pushes a return address to the first return stack in response to a branch to subroutine instruction in the first thread. If the first return stack is full and borrowing is not enabled by the borrow enable indicator, the control circuitry removes an oldest return address from the first return stack and not store the removed oldest return address in the second return stack. If the first return stack is full and borrowing is enabled by the borrow enable indicator and the second thread is not enabled, the control circuitry removes the oldest return address from the first return stack and push the removed oldest return address onto the second return stack.

Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Abstract: A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.

Abstract: A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.

Abstract: A method of operating a multi-thread capable processor system comprising a plurality of processor pipelines is described. The method comprises fetching an instruction comprising an address and selecting an operation mode based on the address of the fetched instruction, the operation mode being selected from at least a lock-step mode and a multi-thread mode. If the operation mode is selected to be the lock-step mode, the method comprises letting at least two processor pipelines of the multi-thread capable processor system execute the instruction in lock-step mode to obtain respective lock-step results, comparing the respective lock-step results against a comparison criterion for determining whether the respective lock-step results match, and, if the respective lock-step results match, determine a matching result from the respective lock-step results, and writing back the matching results.

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Abstract: Upon detecting an occurrence of a watchpoint event for debugging a computer processing system, at least a portion of at least one message in a trace message buffer is flushed when a characteristic of the at least one of the messages matches a specified characteristic.

Abstract: A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode. A method of operating a processor is also disclosed.

Abstract: A method includes etching one or more fluidic channels into a first substrate made of a first material according to a first spatial pattern. The method also includes, after etching the fluidic channels, then separately etching a space in the first substrate according to a different second pattern that includes at least one connection between at least two different portions of the fluidic channels. The method still further includes depositing a different second material into the space. The method yet further includes bonding a different second substrate to the first substrate to enclose the fluidic channels to configure them to contain or pass one or more fluids. For fabricating a Joule-Thomson cooler, the first substrate is made of a first thermally insulating material; the second material is a thermally conducting material; and the second substrate is made of a second thermally insulating material.