Abstract: An integrated circuit includes a buffer circuit, a receiving circuit, and a programmable repeater circuit. The programmable repeater circuit includes a routing input and an enable input. The programmable repeater circuit buffers an input signal received at the routing input from the buffer circuit through a first conductor to generate an output signal that is provided to an input of the receiving circuit through a second conductor only in response to an enable signal at the enable input enabling the programmable repeater circuit.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

Abstract: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.

Abstract: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.

Abstract: Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

Abstract: Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

Abstract: The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity.

Abstract: The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity.

Abstract: A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

Abstract: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.

Abstract: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.

Abstract: An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.

Abstract: Techniques are provided for trimming drive current in output drivers to compensate for process variations, model inaccuracies, and/or an off-target process. The actual output drive current is measured on the integrated circuit (IC) at wafer sort or during a final test. Based on the measured output drive current, the total transistor width that is required in the output driver to meet an I/O standard is calculated. A control block controls trimming transistors that are coupled in parallel with main output drive transistors. The control block adjusts the total width of the output drive transistors to bring the total width as close as possible to the desired width. Each I/O driver on a die can be adjusted individually based on its own drive current characteristics. All I/O drivers on a die can be adjusted by the same transistor width based on a single I/O measurement or on multiple I/O measurements.

Abstract: A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

Abstract: A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.