Abstract: An integrated circuit and associated methods operable therein to provide hardware assist to RAID storage management controllers. The RAID assist integrated circuit offloads a general purpose processor of the storage controller from the responsibility and processing associated with address mapping. RAID geometry and addressing parameters may be stored in a register file or similar storage associated with the RAID assist integrated circuit so as to permit logic therein to automatically map host request parameters to corresponding low level device commands and status. The RAID assist integrated circuit may incorporate scatter/gather list processing features and address mapping features. Queue management features may also be integrated therein to provide buffered queueing of commands and status exchanged between the host system and the storage controller. In addition, host interface features, storage device interface features and RAID redundancy (e.g.

Abstract: A data stream is transferred through a parallel data bus while the read or write strobe is adjusted. The resultant data is compared to the original data to detect errors with each data line of the parallel bus. The results are displayed on a grid whereby the characteristics of each line of the data bus may be visually understood. The characteristic image of the performance of the data bus may be used for debugging the bus, as well as for other uses wherein the performance is very highly characterized.

Abstract: A data stream is transferred through a parallel data bus while the read or write strobe is adjusted. The resultant data is compared to the original data to detect errors with each data line of the parallel bus. The results are displayed on a grid whereby the characteristics of each line of the data bus may be visually understood. The characteristic image of the performance of the data bus may be used for debugging the bus, as well as for other uses wherein the performance is very highly characterized.