Abstract: Examples described herein generally relate to a computer system for generating a knowledge graph storing a plurality of entities and to displaying a topic page for an entity in the knowledge graph. The computer system performs a mining of source documents within an enterprise intranet to determine a plurality of entity names. The computer system generates an entity record within the knowledge graph for a mined entity name based on an entity schema and the source documents. The entity record includes attributes aggregated from the source documents. The computer system receives a curation action on the entity record from a first user. The computer system updates the entity record based on the curation action. The computer system displays an entity page including at least a portion of the attributes to a second user based on permissions of the second user to view the source documents.

Abstract: Examples described herein generally relate to a computer system for generating a knowledge graph storing a plurality of entities and to displaying a topic page for an entity in the knowledge graph. The computer system performs a mining of source documents within an enterprise intranet to determine a plurality of entity names. The computer system generates an entity record within the knowledge graph for a mined entity name based on an entity schema and the source documents. The entity record includes attributes aggregated from the source documents. The computer system receives a curation action on the entity record from a first user. The computer system updates the entity record based on the curation action. The computer system displays an entity page including at least a portion of the attributes to a second user based on permissions of the second user to view the source documents.

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses to determine transmission equalization coefficients (TxEQs) for one or more lanes of a high speed serial link. Embodiments include determining a jitter tolerance for each TxEQ of a plurality of TxEQs for a lane of the link. The jitter tolerance for each TxEQ for the lane is based on a level of jitter induced on the lane to detect a number of errors on the lane; determining a voltage (VOC) margin for each TxEQ for the lane, wherein the voltage margin for the lane is based on a voltage corners test applied to the lane to detect a number of errors on the lane at a high voltage point and a low voltage point; determining a TxEQ that provides maximum jitter tolerance and based on the determined lowest voltage margin; and using the TxEQ for the lane during operation.

Abstract: Various apparatuses and methods to generate a clock signal that controls data operations in an integrated circuit. In an embodiment, a circuit for generating a clock signal that controls data operations in an integrated circuit includes a first clock synthesizer, a divider circuit, and a second clock synthesizer. The first clock synthesizer produces a first signal derived from an external reference signal. The first signal has a first frequency that is greater than a frequency of the external reference signal. The divider circuit divides the frequency of the first signal by N, where N is an integer greater than 1. The divider circuit outputs a second signal having a second frequency which is equal to the first frequency divided by N. The second clock synthesizer couples to the divider circuit for producing the clock signal at a frequency which is an integer multiple of the second signal. The second clock synthesizer also produces a strobe signal.