Abstract: Techniques are provided for determining consequences of an injected fault on a system running a given application program or operating system, in order to measure the software impact of a hardware soft error on the application program/operating system. The application program software is emulated instruction-by-instruction, where source operands are randomly modified before an instruction is executed, and destination operands are randomly modified after an instruction is executed, in order to mimic hardware soft errors. In addition, a program counter is randomly modified after execution of a branch instruction. The resulting consequences of such modifications are monitored such that a fault of an instruction being executed is modeled in order to determine a soft error rate (SER) for a software application program or operating system.

Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.

Abstract: Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor. The initializing mechanism initializes a timer. The initializing mechanism then sends a clock start command to the microprocessor. The clocks on the microprocessor are started. Upon the clocks starting, the timer begins and allows temporary transients, such as voltage droop due to a large instantaneous change in demand for current due to the commencement of clock switching. Responsive to the timer reaching a target value, an interrupt unit sends a system reset interrupt. Responsive to the interrupt unit sending the system reset interrupt, an instruction fetch unit fetches a first instruction. This operation will be deterministic to the state of the rest of the microprocessor memory elements (latches, arrays, et al.).

Abstract: Techniques are provided for determining consequences of an injected fault on a system running a given application program or operating system, in order to measure the software impact of a hardware soft error on the application program/operating system. The application program software is emulated instruction-by-instruction, where source operands are randomly modified before an instruction is executed, and destination operands are randomly modified after an instruction is executed, in order to mimic hardware soft errors. In addition, a program counter is randomly modified after execution of a branch instruction. The resulting consequences of such modifications are monitored such that a fault of an instruction being executed is modeled in order to determine a soft error rate (SER) for a software application program or operating system.

Abstract: Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor. The initializing mechanism initializes a timer. The initializing mechanism then sends a clock start command to the microprocessor. The clocks on the microprocessor are started. Upon the clocks starting, the timer begins and allows temporary transients, such as voltage droop due to a large instantaneous change in demand for current due to the commencement of clock switching. Responsive to the timer reaching a target value, an interrupt unit sends a system reset interrupt. Responsive to the interrupt unit sending the system reset interrupt, an instruction fetch unit fetches a first instruction. This operation will be deterministic to the state of the rest of the microprocessor memory elements (latches, arrays, et al.).

Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.