Abstract: The present invention pertains to carpet and methods of making and recycling carpet. In one aspect, the carpet includes: a primary backing which has a face and a back surface; a plurality of fibers attached to the primary backing and extending from the face of the primary backing and exposed at the back surface of the primary backing; an adhesive composition backing; and an optional secondary backing adjacent to the adhesive backing. The method of making carpet includes extrusion coating the adhesive composition onto the back surface of a primary backing to form the adhesive composition backing. The method of recycling carpet can recover one or more polymeric carpet components.

Abstract: A method and device for coding and marking printing including defining a print image in dot formation of various sizes and locations; determining and providing a set of individual print control instructions for individually controlling a plurality of dot image print head nozzles to form the defined print image at absolute dot positions; and undertaking the individual control instructions to provide a printed image on a printing substrate corresponding to the defined print image, whereby the system allows for calculated adjustment of each dot position without computational limitation during the printing cycle.

Abstract: An infrared light sensor for an infrared light detector (1), including a substrate membrane section (2) and at least two sensor chips (7 to 10), which are fastened next to each other on the substrate membrane section (2) and each comprise a layer element (11) which is produced from pyroelectrically sensitive material and is electrically contacted by a base electrode (12) and a head electrode (13) and is arranged in such that there is a voltage difference in each case between the head electrode (13) and the base electrode (12) of each layer element (11) when the layer elements (11) are irradiated with infrared light; and a coupling line (14 to 16) in each case for two adjacently arranged sensor chips (7 to 10), the coupling line coupling the head electrode (13) of the one sensor chip (7 to 9) and the base electrode (12) of the other sensor chip (8 to 10) to each other in an electrically conductive manner so that the layer elements (11) of the sensor chips (7 to 10) are connected in a series circuit, which has

Abstract: Described herein is a resilient floor covering made from non-vinyl materials. Also disclosed are related methods for manufacturing the resilient floor coverings described herein.

Abstract: The present invention pertains to carpet and methods of making and recycling carpet. In one aspect, the carpet includes: a primary backing which has a face and a back surface; a plurality of fibers attached to the primary backing and extending from the face of the primary backing and exposed at the back surface of the primary backing; an adhesive composition backing; and an optional secondary backing adjacent to the adhesive backing. The method of making carpet includes extrusion coating the adhesive composition onto the back surface of a primary backing to form the adhesive composition backing. The method of recycling carpet can recover one or more polymeric carpet components.

Abstract: An apparatus for detecting radiation has a substrate, a protective housing fitting on the substrate, which has an electrically conductive material and a top facing away from the substrate, and that has an aperture therein. A stack is fitted on the substrate inside the protective housing and includes at least one detector substrate having at least one thermal detector element thereon that converts incoming thermal radiation into an electrical signal, at least one circuit carrier having at least one read circuit for reading out the electrical signal, and at least one cover that covers the detector element. The detector substrate is located between the circuit substrate and the cover. The detector substrate and the cover are arranged on each other such that the detector element of the detector substrate and the cover have at least one first stack cavity of the stack therebetween, the stack cavity being defined by the detector support and the cover.

Abstract: The present invention pertains to carpet and methods of making and recycling carpet. In one aspect, the carpet includes: a primary backing which has a face and a back surface; a plurality of fibers attached to the primary backing and extending from the face of the primary backing and exposed at the back surface of the primary backing; an adhesive composition backing; and an optional secondary backing adjacent to the adhesive backing. The method of making carpet includes extrusion coating the adhesive composition onto the back surface of a primary backing to form the adhesive composition backing. The method of recycling carpet can recover one or more polymeric carpet components.

Abstract: A method and device for coding and marking printing including defining a print image in dot formation of various sizes and locations; determining and providing a set of individual print control instructions for individually controlling a plurality of dot image print head nozzles to form the defined print image at absolute dot positions; and undertaking the individual control instructions to provide a printed image on a printing substrate corresponding to the defined print image, whereby the system allows for calculated adjustment of each dot position without computational limitation during the printing cycle.

Abstract: Techniques are disclosed for providing robust, comprehensive measurement and analysis for optimizing efficiency of compressed air systems. The techniques provided can be implemented, for example, in a network appliance local to the target compressed air system, and/or in a server configured to remotely monitor and evaluate the target system. On-site data logging as well as on-site or remote data analysis can be enabled, along with onboard data consolidation. Meters (e.g., airflow, air pressure, power, and/or acoustic) are deployed at the target system and provide data upon which the analysis is based.

Abstract: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

Abstract: The present invention pertains to carpet and methods of making and recycling carpet. In one aspect, the carpet includes: a primary backing which has a face and a back surface; a plurality of fibers attached to the primary backing and extending from the face of the primary backing and exposed at the back surface of the primary backing; an adhesive composition backing; and an optional secondary backing adjacent to the adhesive backing. The method of making carpet includes extrusion coating the adhesive composition onto the back surface of a primary backing to form the adhesive composition backing. The method of recycling carpet can recover one or more polymeric carpet components.

Abstract: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.

Abstract: An output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. Output drivers are calibrated by generating a first variable count in response to comparing a reference voltage to a first voltage at a calibration terminal when an external load is connected. A first pull-up impedance circuit is varied in response to a first variable count and varying an impedance in a second variable pull-up impedance circuit in response to the first variable count. A second variable count is generated responsive to comparing the reference voltage to a second voltage at a reference node between the second variable pull-up impedance circuit and a serially connected to a variable pull-down impedance circuit. The impedance to the variable pull-down impedance circuit is varied in response to the second variable count. The first and second variable counts for configuring the output drivers are output when a steady state is achieved.

Abstract: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

Abstract: A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path.

Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

Abstract: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

Abstract: A synchronous dynamic random access memory (“SDRAM”) device includes several banks of memory cell coupled to a read data path and a write data path. The read data path includes a read latch that stores a relatively large number of read data bits received in parallel from a bank of memory cells. Groups of the stored read data bits are sequentially selected by a multiplexer and applied to a read data bus. Groups of write data bits are sequentially coupled to the SDRAM device through a write data bus that is separate from the read data bus, and they are sequentially stored in input registers. When the input registers are full, the write data bits are coupled in parallel to a bank of memory cells. The number of bits in the write data bus is preferably a submultiple of the number of bits in the read data bus.