Abstract: Methods, systems, apparatuses, and computer-readable storage mediums described herein are configured to detect anomalous post-authentication behavior/state change(s) with respect to a workload identity. For example, audit logs that specify actions performed with respect to the workload identity of a platform-based identity service, a causing state change(s), while another identity is authenticated with the platform-based identity service, are analyzed. The audit log(s) are analyzed via a model for anomaly prediction based on actions. The model generates an anomaly score indicating a probability whether a particular sequence of the actions is indicative of anomalous behavior/state change(s). A determination is made that an anomalous behavior has occurred based on the anomaly score, and when anomalous behavior has occurred, a mitigation action may be performed that mitigates the anomalous behavior.

Abstract: Technologies are provided for processing data in neural networks. An example method can include processing, by each layer of a neural network, a row in a first stripe of a data input, the row being processed sequentially in a horizontal direction and according to a layer-by-layer sequence; after processing the row, processing, by each layer, subsequent rows in the first stripe on a row-by-row basis, each subsequent row being processed sequentially in the horizontal direction and according to the layer-by-layer sequence; generating an output stripe based on the processing of the row and subsequent rows; processing, by each layer, a second stripe of the data input, each row in the second stripe being processed in the horizontal direction and according to the layer-by-layer sequence, wherein rows in the second stripe are processed on a row-by-row basis; and generating another output stripe based on the processing of the second stripe.

Abstract: A dual-band, tri-band, or higher-order multi-band array of antenna elements, with each element, or subsets of elements, connected to multiple radios at each antenna port. In one embodiment, an array comprises a 128 element Massive MIMO array having 64 horizontally-polarized (H-pol) and 64 vertically-polarized (V-pol) elements configured to provide dual polarization capability over multiple bands to accommodate highly-configurable simultaneous 4G and 5G operation.

Abstract: The present disclosure relates to systems, methods, and computer readable media implemented in connection with an unmanned aerial vehicle (UAV) to navigate a UAV along a desired path. For example, systems disclosed herein identify an anticipatory flight path and identify a plurality of reference points on the flight path relative to a current position of the UAV. The systems described herein may further determine reference angles between a current trajectory of the UAV and the reference points to determine an updated trajectory that the UAV should take to stay close to the identified flight path. The systems described herein may further cause the UAV to accelerate in a lateral direction based on the updated trajectory. The features and functionality of systems disclosed herein enable the UAV to accurately follow a complex path having sharp turns with little or no advanced knowledge of the flight path prior to departure.

Abstract: A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

Abstract: A method of efficiently executing a plurality of processes is described. The method generates, using a predictor, operating constraints for the processes. An operating constraint of the operating constraints is for each process of the processes. The method evaluates possible operating points for each process consistent with the operating constraints and according to a cost function for the processes. The method also determines an operating point for each process based on the evaluating.

Abstract: A method for guiding an aerial system is described. The method includes an act of determining a plurality of reference points at a single time. The method includes one or more of an act of determining a longitudinal acceleration based on one or more of the plurality of reference points or an act of determining a lateral acceleration based on one or more of the plurality of reference points.

Abstract: The present disclosure relates to systems, methods, and computer readable media implemented in connection with an unmanned aerial vehicle (UAV) to navigate a UAV along a desired path. For example, systems disclosed herein identify an anticipatory flight path and identify a plurality of reference points on the flight path relative to a current position of the UAV. The systems described herein may further determine reference angles between a current trajectory of the UAV and the reference points to determine an updated trajectory that the UAV should take to stay close to the identified flight path. The systems described herein may further cause the UAV to accelerate in a lateral direction based on the updated trajectory. The features and functionality of systems disclosed herein enable the UAV to accurately follow a complex path having sharp turns with little or no advanced knowledge of the flight path prior to departure.

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.