Abstract: A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A latch/counter or equivalent is associated with each respective column. A clock supplies clock signal(s) to the counter elements. When the analog ramp equals the pixel value for that column, the latch/counter latches the value. The black level can be pre-set in the latch/counter or can be subtracted separately to reduce fixed pattern noise. The pixels can be oversampled for some number of times, e.g., n=16, to reduce the thermal noise of the sensors. Also, two or more pixels sharing a common sense node may be binned together, and two (or more) pixels having different integration times may be combined to obtain an output signal with enhanced dynamic range.

Abstract: A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses is situated with each microlens covering a plurality of the pixels. The different pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).

Abstract: A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk.

Abstract: A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.

Abstract: An efficient image capture system is disclosed that integrates functions to control a lens including one or more of focus or object distance, zoom, temperature compensation, and stabilization within an image signal processor (ISP) with appropriate algorithms. In particular, the integrated ISP circuitry may control the motion of the focus and zoom optics of an optical assembly, control stabilization, control the flash, provide enhanced functions and features for controlling the zoom and focus lenses to enable enhanced image capture sequences and/or tracking lens data, provide a set of algorithms within the ISP to alter the aspect ratio (both height and width of an image) of the image, for example to compensate for the addition of an anamorphic lens, and integrate an anamorphic lens into the module to alter an image's projected aspect ratio onto the focal plane array.

Abstract: A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A ripple counter or equivalent is associated with each respective column. A clock supplies clock signals to the counter elements. A comparator in each column gates the counter element when the analog ramp equals the pixel value for that column. The contents of the counters are transferred sequentially to a video output bus to produce the digital video signal. Additional black-level readout counter elements can create and store a digital value that corresponds to a dark or black video level. A subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer counter/latches can be employed.

Abstract: A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.

Abstract: A system for capturing an image includes a CMOS imaging system, an image focusing device, and an image control processing system coupled to the CMOS imaging system. The CMOS imaging system has at least one CMOS imager with at least one series of pixels. The image focusing device directs the image on to at least a portion of the at least one series of pixels. The CMOS imager may have two or more series of pixels at least adjacent each other where each of the series of pixels is offset from another one of the series of the pixels by a reciprocal of the total number of series of pixels in the CMOS imager.

Abstract: A bus system which includes two or more voltage-to-current transformers, a common bus, a terminal bus coupled to a voltage source, two or more first switches, and a selection circuit. Each of the voltage-to-current transformers converts a voltage signal to a current signal. The common bus carries the current signals from the voltage-to-current transformers to an output bus. Each of the first switches has a first position where an output from one of the voltage-to-current transformers is coupled to the common bus and a second position where the output is coupled to the terminal bus. The selection circuit is coupled to each of the first switches and controls movement of each of the first switches between the first and second positions.

Abstract: A bus system and an imager for transferring signals from a plurality of signal streams to an output includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output. A method for transferring signals includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to an output.

Abstract: An analog video bus architecture that utilizes the column parallel nature of CMOS imagers and more specifically Active Column Sensors, that eliminates the need for multi-port imagers, by increasing the useable bandwidth of single port imagers. An adaptation of this invention allows for either binning or interpolation of pixel information for increased or decreased resolution along the columns and more specifically for ACS imagers binning or interpolation along the rows. In this bus, the single video bus is replaced by multiple video buses and instead of selecting only one column for reading multiple columns are also pre-selected in-order to pre-charge the video bus. The video buses are then de-multiplexed back on to one port at the desired element rate. This architecture utilizes the column oriented video bus of CMOS imagers. It divides the large video bus capacitance by the number of video buses used. In addition, it allows multiple pixel time constants to precharge the video bus.

Abstract: A system for capturing an image includes a CMOS imaging system, an image focusing device, and an image control processing system coupled to the CMOS imaging system. The CMOS imaging system has at least one CMOS imager with at least one series of pixels. The image focusing device directs the image on to at least a portion of the at least one series of pixels. The CMOS imager may have two or more series of pixels at least adjacent each other where each of the series of pixels is offset from another one of the series of the pixels by a reciprocal of the total number of series of pixels in the CMOS imager.

Abstract: A bus system which includes two or more voltage-to-current transformers, a common bus, a terminal bus coupled to a voltage source, two or more first switches, and a selection circuit. Each of the voltage-to-current transformers converts a voltage signal to a current signal. The common bus carries the current signals from the voltage-to-current transformers to an output bus. Each of the first switches has a first position where an output from one of the voltage-to-current transformers is coupled to the common bus and a second position where the output is coupled to the terminal bus. The selection circuit is coupled to each of the first switches and controls movement of each of the first switches between the first and second positions.

Abstract: A bus system and an imager for transferring signals from a plurality of signal streams to an output includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output. A method for transferring signals includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to an output.