Abstract: An array of light beam emitter sections comprises: a substrate having a surface divided into an array of sections; and a grouping of light emitters disposed at each surface section and configured to emit light beams at different emission angles with respect to the surface. Also disclosed is apparatus for establishing optical communication channels between the array of light beam emitter sections and an array of light detectors. Further disclosed is a method of establishing optical communication channels between the array of light emitter sections and the array of light detectors by mapping at least one light emitter of each grouping with a light detector of the detector array to establish optical communication channels between the arrays based on the mappings.

Abstract: An AC coupling circuit is disclosed herein. An embodiment of the circuit comprises a first differential input and a second differential input. A first resistor is connected between the first differential input and the second differential input. A first capacitor is connected between the first differential input and a first differential output. A second capacitor is connected between the second differential input and a second differential output. A second resistor is connected between the first differential output and a node. A third resistor is connected between the second differential output and the node. A first potential is applied to the node.

Abstract: An array of light beam emitter sections comprises: a substrate having a surface divided into an array of sections; and a grouping of light emitters disposed at each surface section and configured to emit light beams at different emission angles with respect to the surface. Also disclosed is apparatus for establishing optical communication channels between the array of light beam emitter sections and an array of light detectors. Further disclosed is a method of establishing optical communication channels between the array of light emitter sections and the array of light detectors by mapping at least one light emitter of each grouping with a light detector of the detector array to establish optical communication channels between the arrays based on the mappings.

Abstract: An array of light beam emitter sections comprises: a substrate having a surface divided into an array of sections; and a grouping of light emitters disposed at each surface section and configured to emit light beams at different emission angles with respect to the surface. Also disclosed is apparatus for establishing optical communication channels between the array of light beam emitter sections and an array of light detectors. The apparatus comprises a controller coupled to the arrays of emitter sections and detectors for mapping at least one light emitter of each grouping with a light detector of the detector array to establish optical communication channels between the arrays based on the mappings.

Abstract: A system for self-configuring optical communication channels between arrays of emitters and detectors comprises: an array of light emitters; an array of light detectors roughly aligned with the array of light emitters; and self-configuration logic for controlling the light emitters of the emitter array to transmit optical data to the array of light detectors and for monitoring received optical data of the light detectors of the detector array to establish light emitter/detector optical channels between the arrays of light emitters and light detectors based on optical data transmission error rates.

Abstract: A system for configuring fiber optic communication channels between arrays of emitters and detectors comprises: an array of light emitters; an array of light detectors; a bundle of optical fibers disposed between the arrays of light emitters and light detectors for conducting light from the light emitters to the light detectors, wherein the number of optical fibers in the bundle is greater than the number of light emitters in the array and wherein an area cross-section of the bundle of optical fibers overlaps the array of light emitters and the array of light detectors; and logic for mapping at least one emitter to at least one detector to establish at least one optical fiber communication channel between the array of light emitters and the array of light detectors. The system is further operative to monitor data communication over the at least one fiber optic communication channel and to reconfigure the mapping based on the monitored data communications thereof.

Abstract: A system for configuring fiber optic communication channels between arrays of emitters and detectors comprises: an array of light emitters; an array of light detectors; a bundle of optical fibers disposed between the arrays of light emitters and light detectors for conducting light from the light emitters to the light detectors, wherein a diameter of each optical fiber in the bundle is greater than a diameter of light emitted from each light emitter in the array, and wherein an area cross-section of the bundle of optical fibers overlaps the array of light emitters and the array of light detectors; and logic for mapping at least one emitter to at least one detector to establish at least one fiber optic communication channel between the array of light emitters and the array of light detectors. A counterpart method is also disclosed.

Abstract: Apparatus for connecting an interconnecting cable between first and second printed circuit (PC) boards comprises: a base member disposed on a side of the first PC board for fixedly attaching one end of the interconnecting cable to the first PC board; a first connector attached to the other end of the interconnecting cable; a second connector disposed on a side of the second PC board; and a spring member attached to the base member for supporting the first connector away from the side of the first PC board, the spring member operative to force the first connector against the side of the second PC board to cause slidable engagement of the first and second connectors when one of the first and second PC boards is slid past the other of the first and second PC boards.

Abstract: A circuit for reducing capacitive coupling between a culprit and a victim signal line is provided which comprises two inverters, a n-channel FET connected as a capacitor, and a p-channel FET connected as a capacitor. The input of both inverters are connected to the culprit line. The first inverter is designed to respond to high-to-low transition on the culprit line more rapidly than a low-to-high transition. The output of the first inverter is connected to the drain and source of the n-channel FET. The gate of the n-channel FET is connected to the victim line. The second inverter is designed to respond to low-to-high transition on the culprit line more rapidly than a high-to-low transition. The output of the second inverter is connected to the drain and source of the p-channel FET. The gate of the p-channel FET is connected to the victim line.

Abstract: A register selection system increases a speed for selection of memory registers when selection is based upon a constant K defined by a sum of two numbers. The register selection system includes a specialized predecoder interconnected with a specialized decode array. The predecoder has first and second address inputs. The predecoder is configured to process first and second address values each of width n on the first and second address inputs respectively in order to produce first, second, third, and fourth predecoded values of width n on respective predecoder outputs. The first, second, third, and fourth predecoded values have respective widths of n+1, n, n, n-1. The decode array, which is connected to the predecoder outputs, is configured to receive the predecoded values. The decode array has 2.sup.n+1 register select outputs corresponding respectively with registers.

Abstract: The present invention relates to computer systems utilizing a TLB with variable sized pages. This invention detects conflicts between address tags stored in the TLB and a prospective address tag. In particular this invention detects conflicts when the prospective tag represents an address space that overlaps, wholly includes or is included in the address space represented by a tag stored in the TLB. By detecting tag conflicts utilizing hardware, a tremendous performance gain is achieved over systems utilizing prior art software systems.

Abstract: Disclosed herein are methods and apparatus for performing magnitude comparisons within a shift-merge unit (SMU). A programmable or partially programmable Manchester carry chain is used to perform each comparison. The Manchester carry chains are programmed using the bits of mask markers and are constructed so as to make a comparison with respect to a given mask condition and position marker which are constants. An implementation in dual rail dynamic CMOS logic avoids the necessity of input inversions, and allows construction of more compact Manchester carry chain circuitry. The size of an SMU will therefore be determined by mask marker routings rather than transistor count. When shorted, opened, and/or redundant transistors, and/or transistors programmed with constants are optimized out of constructed Manchester carry chains, the mask marker bits of a dual rail SMU will have equal fanouts, thereby preventing clock skew.

Abstract: Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates. Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates. Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed.

Abstract: Vector logic is implemented by pipelining logic stages comprised of dynamic mousetrap logic gates. A novel pipeline latch is associated with each logic stage of the pipeline. Each pipeline latch has a latch reset mechanism, an input trigger mechanism, a disabling mechanism, a flip-flop mechanism, an output gating mechanism, and a latch enable pull-up mechanism. Moreover, the logic stages are alternately clocked. While the even numbered stages are receiving a high clock signal for instigating propagation, the odd numbered stages are receiving a low clock signal for instigating precharging, and vice versa. The high and low clock times for each stage is substantially equivalent. Due to inherent manufacturing inequalities, clock asymmetry results. An advantaged and disadvantaged phase arises. Because of the novel latch and associated method, pipeline stages operating in the disadvantaged phase can steal time from those operating in the advantaged phase. Further, no minimum clock frequency is required.

Abstract: A dynamic mousetrap logic gate implements a self-timed monotonic logic progression via a novel vector logic method. In the vector logic method, a vector logic variable is defined by a plurality of vector components situated on respective logic paths. Boolean as well as non-Boolean variables can be represented. Further, timing information is encoded in the vector logic variable itself by defining the vector logic variable as invalid when all the vector components currently exhibit a logic low and by defining the vector logic variable as valid when a subset of the vector components exhibits a logic high. With a plurality of valid vector logic states, subsets defining valid vector logic states are nonoverlapping. The mousetrap logic gate comprises a plurality of gate components in parallel, corresponding with each output vector component. Each gate component has an arming mechanism, a ladder logic, and an inverting buffer mechanism.

Abstract: A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed logic evaluation on vector inputs to derive a vector output. An evaluation done detector monitors the output of the logic block and determines when the vector output is valid. An edge detector detects the rising and falling edges of an arbitrary periodic timing signal. Finally, a logic block clock generator is set by the edge detector and reset by the evaluation done detector so as to provide precharging signals to the logic block, thereby defining respective precharge periods, and to provide evaluation periods for the self-timed logic evaluations in the logic block. In a specific implementation, the speed of logic evaluations is twice the speed of the system clock.

Abstract: The adverse effects of charge sharing in dynamic logic gates are mitigated. The dynamic logic gates have an inverting buffer for providing a gate output, an arming mechanism for precharging the inverting buffer input, and ladder logic for receiving a gate input and for discharging the inverting buffer input to ground. The ladder logic comprises a plurality of transistors connected in ladder-like manner. In a first embodiment, the interstitial space between parallel transistor gates in the ladder logic is reduced so as to minimize parasitic capacitances. In a second embodiment, the parasitic capacitance of at a converging node defined by at least three converging transistors is minimized by disposing the transistor gates adjacent one another so that the transistors share a common interstitial space with a region of each transistor gate adjacent a region of each of the other remaining gates.

Abstract: A memory device having a plurality of read ports which can be dumped simultaneously without affecting the data stored in the memory cells of the memory device. The read ports of the memory device of the invention include dump circuits comprising a pair of small NFETs which logically AND the values stored in the memory cell with a READ input signal and then pull low a precharged output line only when both of these signals are true. Each such read port dump circuit is electrically isolated from the others so that multiple read ports can be dumped simultaneously with affecting the data stored in the memory device. Also, by placing only a single transistor in the read port discharge path, the dump circuit may be small and have a minimal impact on write setup time in accordance with the invention.

Abstract: A content addressable memory (CAM) access system and method having self-timing and built-in margin test features. The present invention includes a compare array which has multiple comparator paths. The comparator paths generate multiple mismatch indications after receiving a system clock signal. The present invention also includes a row driver which receives the mismatch indications produced by the compare array after receiving a Tclock signal. The row driver generates multiple row enables based on the mismatch indications. The Tclock signal is generated only after the mismatch indications are valid. Thus, the row driver always receives valid mismatch indications. According to the present invention, the Tclock signal is generated by simulating a worst case path through the compare array. The worst case path produces a dummy mismatch indication.

Abstract: A logic system uses novel mousetrap logic gates which implement novel vector logic. In a vector logic system, any number of valid vector logic states and one invalid vector logic state is defined by the logic signals on a set of logic paths. An invalid vector logic state is defined as the case when all logic paths exhibit a low logic signal. A valid vector logic state can be defined in a variety of ways. In the preferred embodiment, a valid vector logic state is defined as the case when one and only one of said logic paths exhibits a high logic signal. Furthermore, mousetrap logic gates, which can be connected directly in series and/or parallel to collectively perform logic functions, implement the foregoing logic scheme. Each mousetrap logic gate has an arming mechanism, ladder logic, and a buffer. A precharge is supplied by the arming mechanism to the buffer. Incoming logic is operated upon by the ladder logic and used to trigger the precharged buffer.