Patents by Inventor Jeffry Gonion
Jeffry Gonion has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9875214Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory.Type: GrantFiled: July 31, 2015Date of Patent: January 23, 2018Assignees: ARM Limited, Apple, Inc.Inventors: Mbou Eyole, Nigel John Stephens, Jeffry Gonion, Alex Klaiber, Charles Tucker
-
Publication number: 20170031865Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Inventors: Mbou EYOLE, Nigel John STEPHENS, Jeffry GONION, Alex KLAIBER, Charles TUCKER
-
Patent number: 9257101Abstract: A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use.Type: GrantFiled: September 14, 2012Date of Patent: February 9, 2016Assignee: APPLE INC.Inventors: Ian Hendry, Jeffry Gonion, Jeremy Sandmel
-
Patent number: 8868847Abstract: Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit having a plurality of cores. A cache memory management system may be associated with each core that includes a cache memory device configured to store a plurality of cache lines, a page status table configured to track pages of memory stored in the cache memory device and to indicate a status of each of the tracked pages of memory, and a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request based at least in part on the status of one of the tracked pages in the page status table.Type: GrantFiled: March 11, 2009Date of Patent: October 21, 2014Assignee: Apple Inc.Inventor: Jeffry Gonion
-
Patent number: 8856456Abstract: Systems, methods, and devices for efficient cache coherence between memory-sharing devices are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block tracking entries (BTEs). Each BTE may indicate whether groups of one or more cache lines of a block of memory could potentially be in use by another memory-sharing device. By way of example, a memory-sharing device may employ a table of BTEs that each has several cache status entries. When a cache status entry indicates that none of a group of one or more cache lines could possibly be in use by another memory-sharing device, a snoop request for any cache lines of that group may be suppressed without jeopardizing cache coherence.Type: GrantFiled: June 9, 2011Date of Patent: October 7, 2014Assignee: Apple Inc.Inventors: Ian C. Hendry, Jeffry Gonion
-
Patent number: 8799553Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.Type: GrantFiled: September 30, 2010Date of Patent: August 5, 2014Assignee: Apple Inc.Inventors: Ian Hendry, Rajabali Koduri, Jeffry Gonion
-
Publication number: 20130009975Abstract: A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: APPLE INC.Inventors: Ian Hendry, Jeffry Gonion, Jeremy Sandmel
-
Publication number: 20120317362Abstract: Systems, methods, and devices for efficient cache coherence between memory-sharing devices are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block tracking entries (BTEs). Each BTE may indicate whether groups of one or more cache lines of a block of memory could potentially be in use by another memory-sharing device. By way of example, a memory-sharing device may employ a table of BTEs that each has several cache status entries. When a cache status entry indicates that none of a group of one or more cache lines could possibly be in use by another memory-sharing device, a snoop request for any cache lines of that group may be suppressed without jeopardizing cache coherence.Type: ApplicationFiled: June 9, 2011Publication date: December 13, 2012Applicant: APPLE INC.Inventors: Ian C. Hendry, Jeffry Gonion
-
Patent number: 8310494Abstract: A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use.Type: GrantFiled: November 24, 2008Date of Patent: November 13, 2012Assignee: Apple Inc.Inventors: Ian Hendry, Jeffry Gonion, Jeremy Sandmel
-
Publication number: 20110252180Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active.Type: ApplicationFiled: September 30, 2010Publication date: October 13, 2011Applicant: APPLE INC.Inventors: Ian Hendry, Rajabali Koduri, Jeffry Gonion
-
Publication number: 20100235586Abstract: Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit having a plurality of cores. A cache memory management system may be associated with each core that includes a cache memory device configured to store a plurality of cache lines, a page status table configured to track pages of memory stored in the cache memory device and to indicate a status of each of the tracked pages of memory, and a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request based at least in part on the status of one of the tracked pages in the page status table.Type: ApplicationFiled: March 11, 2009Publication date: September 16, 2010Applicant: APPLE INC.Inventor: Jeffry Gonion
-
Publication number: 20100079445Abstract: A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use.Type: ApplicationFiled: November 24, 2008Publication date: April 1, 2010Applicant: Apple Inc.Inventors: Ian Hendry, Jeffry Gonion, Jeremy Sandmel
-
Publication number: 20060004996Abstract: A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.Type: ApplicationFiled: September 1, 2005Publication date: January 5, 2006Inventor: Jeffry Gonion