Abstract: A pipeline computer architecture having two interconnected microengines operating simultaneously in an instruction preparation unit of a pipeline computer system. Each microengine operates on the same portion or different portions of an instruction concurrently within the same clock cycle. To assure coordination, one microengine is declared the executive or attribute generator and the other the main microengine. The main microengine generates routines to control the instruction preparation unit hardware. The executive microengine prepares the next tank in parallel and supplies arguments to the main microengine as the main microengine generates its current routine. At the completion of a routine performed by the main microengine, it signals the executive microengine to obtain the next task and associated parameters.