Patents by Inventor JEGWAN HWANG

JEGWAN HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955509
    Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihyung Kim, Jeonghoon Ahn, Jaehee Oh, Shaofeng Ding, Wonji Park, Jegwan Hwang
  • Publication number: 20230260893
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a transistor provided on the first surface of the semiconductor substrate; a power rail provided on the first surface of the semiconductor substrate and electrically connected to the transistor; first and second lower interconnection lines provided on the second surface of the semiconductor substrate and spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate; a penetration via penetrating the semiconductor substrate and connecting a corresponding one of the first and second lower interconnection lines to the power rail; and a capacitor provided between and electrically connected to the first and second lower interconnection lines.
    Type: Application
    Filed: October 27, 2022
    Publication date: August 17, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JIHYUNG KIM, JAEHEE OH, JEGWAN HWANG, SHAOFENG DING, WON JI PARK, JEONG HOON AHN, YUN KI CHOI
  • Publication number: 20230154894
    Abstract: A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.
    Type: Application
    Filed: July 12, 2022
    Publication date: May 18, 2023
    Inventors: Jegwan HWANG, Jihyung KIM, Jeong Hoon AHN, Jaehee OH, Shaofeng DING, Won Ji PARK, WooSeong JANG, Seokjun HONG
  • Publication number: 20220384563
    Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: December 1, 2022
    Inventors: JIHYUNG KIM, JEONGHOON AHN, JAEHEE OH, SHAOFENG DING, WONJI PARK, JEGWAN HWANG