Abstract: A trigger sense circuit includes a pseudo-differential comparator circuit in signal communication with a pixel array. The pseudo-differential comparator circuit includes a first input in signal communication with a reference pixel group included in the pixel array to receive a pixel reference voltage, and a second input in signal communication with a target pixel group included in the pixel array to receive a pixel target voltage. The pseudo-differential comparator circuit is configured to selectively operate in a calibration mode to remove false trigger events and a comparison mode to detect at least one overheated pixel included in the target pixel group.

Abstract: A device includes multiple row power lines and multiple row control lines arranged in rows, where each row control line corresponds to one of the row power lines. The device also includes multiple column power lines arranged in columns. The device further includes multiple unit cells, where each unit cell is coupled to one of the row power lines and one of the row control lines and selectively coupled to one of the column power lines. In addition, the device includes multiple row power switches and multiple column power switches arranged in pairs, where each pair includes one of the row power switches and one of the column power switches. Each pair is configured to selectively (i) connect a corresponding one of the rows and a corresponding one of the columns or (ii) isolate the corresponding one row and the corresponding one column from each other.

Abstract: A dual mode focal plane array having a readout integrated circuit (IC) is provided herein that is electrically switchable between a first mode (e.g., direction injection mode) and a second mode (e.g., buffered direction injection) based in part on a level of a detection current. The IC includes a switching network disposed between an operational amplifier and a switching element to transition the IC between the first and second mode responsive to a control signal. The control signal can include instructions to open or close the one or more switches of the switching network and thus transition the IC between the different modes.

Abstract: Methods and apparatus for a dual mode focal plane array having a background module including a first capacitor to integrate a first signal for a first amount of time, wherein the first signal comprises a background signal, and a signal module including a second capacitor to integrate a second signal for a second amount of time, wherein the second signal comprises a signal of interest and the background signal, wherein the first and second capacitors have impedance values in a first ratio, and wherein the first amount of time and the second amount of time define a second ratio corresponding to the first ratio.

Abstract: Methods and apparatus for a dual mode focal plane array having a background module including a first capacitor to integrate a first signal for a first amount of time, wherein the first signal comprises a background signal, and a signal module including a second capacitor to integrate a second signal for a second amount of time, wherein the second signal comprises a signal of interest and the background signal, wherein the first and second capacitors have impedance values in a first ratio, and wherein the first amount of time and the second amount of time define a second ratio corresponding to the first ratio.

Abstract: A dual mode focal plane array having a readout integrated circuit (IC) is provided herein that is electrically switchable between a first mode (e.g., direction injection mode) and a second mode (e.g., buffered direction injection) based in part on a level of a detection current. The IC includes a switching network disposed between an operational amplifier and a switching element to transition the IC between the first and second mode responsive to a control signal. The control signal can include instructions to open or close the one or more switches of the switching network and thus transition the IC between the different modes.

Abstract: An imaging device in accordance with the present disclosure comprises of a pixelated array of semiconductor detector elements, each of the pixels in the array having an in-pixel integrated circuit, the integrated circuit having a comparator, a readout decoder block, and an address arbitration control block. The readout decoder block reads out the integrated signals of the pixels. The address arbitration control block determines the pixel address of the pixels charging beyond a threshold voltage, the threshold exceedance determined by the comparator. The addressed pixels are provided a timestamp for each of the pixels integrating beyond the threshold voltage, the timestamp provided by an off-pixel time-to-digital converter (TDC), the value of the timestamp corresponding with the accumulated charge of the pixel.

Abstract: An imaging device is disclosed, the device comprising a pixelated array of semiconductor detector elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit comprising a passive signal path and an active signal path. The active path provides consecutive frame imaging and the active path detects the location of transient events. The device further comprising a readout decoder block, the readout decoder block controlling operation of the passive paths. Additionally the device comprises of an address arbitration control block, the address arbitration control block controlling operation of the active paths, wherein the address arbitration control block readout of the active paths is independent of readout of the passive paths.

Abstract: An imaging device is disclosed, the device comprising a pixelated array of semiconductor detector elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit comprising a passive signal path and an active signal path. The active path provides consecutive frame imaging and the active path detects the location of transient events. The device further comprising a readout decoder block, the readout decoder block controlling operation of the passive paths. Additionally the device comprises of an address arbitration control block, the address arbitration control block controlling operation of the active paths, wherein the address arbitration control block readout of the active paths is independent of readout of the passive paths.

Abstract: An imaging device in accordance with the present disclosure comprises of a pixelated array of semiconductor detector elements, each of the pixels in the array having an in-pixel integrated circuit, the integrated circuit having a comparator, a readout decoder block, and an address arbitration control block. The readout decoder block reads out the integrated signals of the pixels. The address arbitration control block determines the pixel address of the pixels charging beyond a threshold voltage, the threshold exceedance determined by the comparator. The addressed pixels are provided a timestamp for each of the pixels integrating beyond the threshold voltage, the timestamp provided by an off-pixel time-to-digital converter (TDC), the value of the timestamp corresponding with the accumulated charge of the pixel.

Abstract: An imaging device is disclosed, the device comprising a pixelated array of semiconductor elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit comprising a passive signal path and an active signal path. The passive path provides consecutive frame imaging and the active path detects the location of transient events. The device further comprising a readout decoder block, the readout decoder block controlling operation of the passive paths. Additionally, the device comprises of an address arbitration control block, the address arbitration control block controlling operation of the active paths, wherein the address arbitration control block readout of the active paths are independent of readout of the integrated signal readout from the passive paths.

Abstract: An imaging device is disclosed, the device comprising a pixelated array of semiconductor detector elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit comprising a passive signal path and an active signal path. The active path provides consecutive frame imaging and the active path detects the location of transient events. The device further comprising a readout decoder block, the readout decoder block controlling operation of the passive paths. Additionally the device comprises of an address arbitration control block, the address arbitration control block controlling operation of the active paths, wherein the address arbitration control block readout of the active paths is independent of readout of the passive paths.

Abstract: Methods and devices for a multi-mode CMOS image sensor are presented. In one respect, the methods can provide varying at least one of a plurality of control signals of a pixel of a CMOS image sensor, where the pixel is operable in a linear mode, logarithmic mode, and floating point mode. The pixel may include a plurality of transistors and a photodetector coupled thereto. Using a plurality of control signals, the mode of the pixel can change between a linear mode, a logarithmic mode, and a floating point mode.