Abstract: A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Abstract: A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

Abstract: A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode.

Abstract: A voltage detecting circuit includes first and second reference voltage generating circuits. The first reference voltage generating circuit provides a reference voltage during a normal operation mode. The second reference voltage generating circuit provides a reference voltage during a test mode. A comparison voltage generating circuit is also included and provides a comparison voltage during both modes in response to a boosted voltage. A differential amplifier circuit is further included in the voltage detecting circuit. The differential amplifier generates an amplified difference signal that is used to generate a voltage level detection signal. The voltage level detection signal controls a pumping operation for generating the boosted voltage level. A bypass circuit may also be provided to lower a detected boosted voltage level and allow operation at lower voltage levels.

Abstract: A voltage detecting circuit includes a first voltage generator that provides a reference voltage, a second voltage generator that provides a comparison voltage in response to a boosted voltage, and a differential amplifier that provides an amplified difference signal to generate a voltage level detection signal in response to a voltage difference between the reference voltage and the comparison voltage. A bypass circuit is coupled to the amplified signal to detect a target VPP level suitable for a test mode by providing a current path in response to the comparison voltage when the comparison voltage reaches a predetermined level. The voltage detecting circuit thereby allows a precise and stable detecting operation to be performed regardless of the operation mode or process or temperature variations.

Abstract: Disclosed is a semiconductor memory device having a master fuse circuit, and an address storage and decoding circuit. The address storage and decoding circuit stores address information to assign a defective main cell of main cells, and receives current address information in response to switch control signals. During a burn-in test mode for the main cells, the master fuse circuit generates the switch control signals in response to a bum-in test signal indicating the bum-in test, for shutting the address information off not to be provided to the address storage and decoding circuit, regardless of a connected state of the master fuse.

Abstract: A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region, so that no contacts are formed directly between the memory cell array region and the bit line equalization region.

Abstract: A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

Abstract: A semiconductor memory device including a redundancy circuit having latch cells is provided. In the semiconductor memory device, memory cells are selected in memory cell blocks each having a plurality of memory cells arrayed in columns and rows. Data of the selected memory cells is input to or output from the memory cell blocks via data lines. The semiconductor memory device includes a row decoder, a sub word line driver, latch cells, fuse boxes, a latch cell control unit, and a switch unit. The row decoder decodes a row address and generates a word line enable signal for selecting the word lines of a group of memory cells among memory cells. The sub word line driver is connected to the word line enable signal, and drives the selected memory cells. The latch cells are arranged along the data lines. Each of the fuse boxes has a plurality of fuses which are programmed in accordance with a defective cell address in the memory cell block.

Abstract: A voltage detecting circuit includes first and second reference voltage generating circuits. The first reference voltage generating circuit provides a reference voltage during a normal operation mode. The second reference voltage generating circuit provides a reference voltage during a test mode. A comparison voltage generating circuit is also included and provides a comparison voltage during both modes in response to a boosted voltage. A differential amplifier circuit is further included in the voltage detecting circuit. The differential amplifier generates an amplified difference signal that is used to generate a voltage level detection signal. The voltage level detection signal controls a pumping operation for generating the boosted voltage level. A bypass circuit may also be provided to lower a detected boosted voltage level and allow operation at lower voltage levels.

Abstract: A voltage detecting circuit includes a first voltage generator that provides a reference voltage, a second voltage generator that provides a comparison voltage in response to a boosted voltage, and a differential amplifier that provides an amplified difference signal to generate a voltage level detection signal in response to a voltage difference between the reference voltage and the comparison voltage. A bypass circuit is coupled to the amplified signal to detect a target VPP level suitable for a test mode by providing a current path in response to the comparison voltage when the comparison voltage reaches a predetermined level. The voltage detecting circuit thereby allows a precise and stable detecting operation to be performed regardless of the operation mode or process or temperature variations.

Abstract: A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line extending over the impurity region supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region.

Abstract: A semiconductor memory device having a row redundancy scheme in which the time to enable a word line during a normal path is less than that of a conventional device, to enhance the operation speed of a memory chip, and the number of common redundancies are maximized to enhance the redundancy capability, and a method for curing a defective cell. The semiconductor memory device has a plurality of global blocks, each of which includes a plurality of unit matrixes having a normal block and a redundancy block, a normal division word line driver, a redundancy division word line driver, a main decoder and an auxiliary decoder. In the main decoder, an output signal is selectively activated according to a row address signal regardless of using the redundancy cell.

Abstract: Integrated circuit memory devices include one or more input receivers that have a reference voltage input terminal. A conductor electrically couples the reference voltage input terminals to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. Accordingly, the capacitor may reduce fluctuations or noise in the reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. A reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.

Abstract: Integrated circuit memory devices include first and second spaced-apart memory banks in an integrated circuit substrate. A pad block in the integrated circuit substrate is located between the first and second spaced-apart memory banks. An input/output block in the integrated circuit substrate is connected to the pad block to receive input data from external of the integrated circuit memory device via the pad block and to transmit output data to external of the integrated circuit memory device via the pad block. A delay locked loop in the integrated circuit substrate is responsive to an external clock signal to generate an internal clock signal. An interface logic block in the integrated circuit substrate is responsive to the internal clock signal to control the first and second memory banks and the input/output block in response to the internal clock signal. A single data shift block in the integrated circuit substrate is located between the pad block and one of the first and second spaced-apart memory banks.

Abstract: Integrated circuit memory devices can reduce write time during a write cycle of a parallel bit test mode. The memory devices include a simultaneous column select line activation circuit that simultaneously activates at least two of the plurality of column select lines during a write cycle of a parallel bit test mode. Therefore, during the write cycle, at least two bit lines are simultaneously connected to one input and output line since at least two column select lines are simultaneously activated by the simultaneous column select line activation circuit. Accordingly, data is simultaneously written to the memory cells connected to at least two bit lines through the input and output line.

Abstract: A high-density semiconductor memory device may be provided with redundant memory, so that it is capable of repairing defects generated in a normal memory cell array by using a spare memory cell array which has a plurality of sub memory cell arrays, split word line driver blocks and sense amps. The spare memory cell array includes a plurality of unit spare mats, each having a given number of the sub memory cell arrays, split word line driver blocks, spare sense amps, and a corresponding spare column decoder. The spare memory cell array further includes a plurality of spare row decoders. A control unit is provided for controlling the split word line driver blocks included in each of the unit spare mats in response to given address signals.

Abstract: A semiconductor memory device includes a sub-wordline and a bit line connected to a memory cell, a sub-wordline driver for signaling the sub-wordline, and a main word decoder and a sub-word decoder, for selecting the sub-wordline driver in response to an external input address signal, wherein the wordline driver includes an NMOS transistor switch connected between a main wordline which is an output of the main word decoder and the sub-wordline, and wherein the logic "high" voltage level of a first control signal which controls the switch is lower than that of a signal output to the sub-wordline. The semiconductor memory device having the sub-wordline driver allows the internal power supply voltage to be used as the power supply voltage of the main word decoder. Accordingly, the reliability of a gate oxide film of a transistor constituting the main word decoder is improved, which lengthens the life of the semiconductor memory device.

Abstract: A semiconductor memory device is tested by sequentially coupling a plurality of global input/output lines to a comparator which compares data bits from the global input/output lines sequentially rather than in parallel so as to reduce the number of output sense amplifiers. This reduces both the chip area, and the excessive current consumption caused by large numbers of sense amplifiers operating in parallel. The memory device includes a plurality of global input/output lines coupled to a memory cell array to receive data from the memory cell array. A global line select circuit generates sequential global line select signals during a test operation. A plurality of switch circuits selectively couples data from the global input/output lines to a sense amplifier responsive to the global line select signals. A comparator coupled to the output port of the sense amplifier sequentially compares a sequence of test data output from the sense amplifier and generates a result signal during the test operation.

Abstract: A circuit and method are shown for controlling a redundant memory cell of an integrated memory circuit. The circuit includes a decoder, a precharge enable unit, a redundant controller, a redundant enable signal generator, and a redundant memory cell array. The precharge enable unit is connected to the decoder, and responds to a precharge enable signal by precharging the output terminal of decoder. The decoder responds to a first row address signal by discharging the output terminal of the decoder unless the value of the row address signal corresponds to a programmed address of the decoder. The redundant enable signal generator samples the voltage level of the output terminal of the decoder under control of a redundant control signal of the redundant controller in order to generate a redundant cell enable signal.