Patents by Inventor Jelena Radumilo-Franklin

Jelena Radumilo-Franklin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9202001
    Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a defined sequence of rats within the assigned bundle. The method may also include routing the plurality of rats between the one or more terminals, based upon, at least in part, the defined sequence.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 1, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Brett Allen Neal, Donald Keith Morgan, Jelena Radumilo-Franklin
  • Patent number: 8910105
    Abstract: The present disclosure relates to a method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may also include generating an independent breakout of the plurality of rats from a source end and a target end of the bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a defined sequence of rats within the assigned bundle based upon, at least in part, the source end of the bundle. The method may additionally include generating a costed sequence breakout at the target end of the bundle, based upon, at least in part, a costed sequence analysis. The method may also include determining if the costed sequence breakout meets at least one criteria associated with the electronic design.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 9, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Brett Allen Neal, Jelena Radumilo-Franklin
  • Patent number: 8726222
    Abstract: A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: May 13, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Sean Bergan, Joseph Dexter Smedley, Paul S. Musto, Brett Allen Neal, Richard Allen Woodward, Jr., Jelena Radumilo-Franklin, Frank Farmar, Gregory M. Horlick
  • Patent number: 8464196
    Abstract: A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: June 11, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Sean Bergan, Joseph Dexter Smedley, Paul S. Musto, Brett Allen Neal, Richard Allen Woodward, Jr., Jelena Radumilo-Franklin, Frank Farmar, Gregory M. Horlick
  • Patent number: 8250514
    Abstract: A routing method for a multilayer circuit design layout that has a set of possible preferred local routing directions and a default preferred routing direction for each layer. The method receives a set of user specified constraints on routing directions for particular regions of the design layout. The method tessellates the available routing space into separate tiles and automatically defines a preferred local routing direction for each tile based on the user specified constraints. The set of user specified constraints includes user designated flows, locked etches, “etch keep-out” areas, user “planned” data, etc. A routing method for a multilayer design layout that receives a first set of user specified preferred routing directions for particular regions of the multilayer design layout. The method tessellates the available routing space into separate tiles and automatically defines a second preferred local routing direction for each tile based on the user specified preferred routing directions.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: August 21, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Randall Lawson, Jelena Radumilo-Franklin
  • Patent number: 7761836
    Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: July 20, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Sean Bergan, Charles W. Grant, Glendine Kingsbury, Randall Lawson, Jelena Radumilo-Franklin, Kota Sujan Reddy, Steve Russo, William Schilp, Davis Tsai, Keith Woodward, Richard Woodward, Jia Wu