Abstract: A semiconductor structure includes a conductive bump disposed between a substrate and a board; an isolation member disposed over the board and surrounding the conductive bump and the substrate; a metallic member disposed between the isolation member and the conductive bump; and a solder disposed between the substrate and the board and configured to attach the metallic member to the substrate and the board. A method of manufacturing a semiconductor structure includes disposing a first solder on a first surface of a substrate; disposing a metallic member to the first surface of the substrate by the first solder; disposing a second solder on a board; and bonding the metallic member to the board by the second solder.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for electronic devices with tactile keyboards. An example electronic device includes a tactile keyboard having a plurality of rows of keys; a printed circuit board; a first row of switches on the printed circuit board, a first row of the plurality of rows of keys to interact with the first row of switches; and a second row of switches on a component adjacent to the printed circuit board, a second row of the plurality of rows of keys to interact with the second row of switches.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed on a first side of a substrate. A second via is disposed on the first side of the substrate and is laterally separated from the first via. An interconnect wire vertically contacts the second via. A through-substrate via (TSV) extends through the substrate to physically contact one or more of the second via and the interconnect wire. The first via has a first width and the second via has a second width. The second width is between approximately 2,000% and approximately 5,000% larger than the first width.

Abstract: Aspects of the disclosure relate to the field of semiconductor devices, including methods and systems for manufacturing semiconductor devices. More particularly, semiconductor structures comprise a dipole layer, which can be formed from a metal and carbon containing layer. Further described are related methods, deposition systems, and devices.

Abstract: An artificial intelligence (AI)-enabled device including a sensor unit, an AI analysis unit, and an action execution unit, for detecting and monitoring objects and their activities within an operating field, is provided. The sensor unit captures multi-modal sensor data elements including sound, image, thermal, radio wave, and other environmental data associated with the objects along with timing data in the operating field. The AI analysis unit includes one or more AI analyzers that, in communication with an AI data library, receive and locally analyze each and an aggregate of the multi-modal sensor data elements. Based on the analysis, the AI analyzers distinguish between the objects detected and identified in the operating field, distinguish non-related sensor data, determine and monitor the activities of the identified objects, and generate and validate activity data from the activities. The action execution unit executes one or more actions in real time based on the validation.

Abstract: A method for improving hue of recycled bis-2-hydroxylethyl terephthalate by using ionic liquids including providing a recycled polyester fabric; using a chemical de-polymerization liquid to chemically de-polymerize the recycled polyester fabric to form a de-polymerization product; mixing the de-polymerization product with water to form an aqueous phase liquid; dispersing an ionic liquid impurity adsorption material into the aqueous phase liquid to adsorb impurities originally present in the recycled polyester fabric.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: An electronic apparatus with a two-way cable connection construction is provided. The electronic apparatus includes a casing kit and an electronic device. The casing kit includes a casing, a main circuit board and an auxiliary circuit board. The main circuit board and the auxiliary circuit board are disposed inside the casing. The auxiliary circuit board and the main circuit board are electrically connected to each other and non-coplanar with each other. When the electronic device is inserted into a mounting slot of the casing along a first direction, a mating electrical connector of the electronic device is connected to a first electrical connector of the auxiliary circuit board. When the electronic device is inserted into the mounting slot of the casing along a second direction opposite to the first direction, the mating electrical connector of the electronic device is connected to a second electrical connector of the auxiliary circuit board.

Abstract: Methods, systems, and devices for wireless communications are described. A station (STA) may receive a first signal including an indication of a set of frequency channels for a set of target wake time (TWT) sessions that recur according to a service interval. In some examples, the first signal may indicate a respective frequency channel of the set of frequency channels for each TWT session of the set of target wake time sessions. Each TWT session of the set of TWT sessions may have an associated service period that the STA may be in an awake state. The STA may switch, for the first TWT session, from the first frequency channel to the second frequency channel. In some examples, based on the switching, the STA may communicate a signal during a service period associated with the first TWT session over the second frequency channel.

Abstract: A stress modulating device including a semiconductor substrate, a first insulating layer formed over a first side of the semiconductor substrate, a second insulating layer formed over the first insulating layer, a third insulating layer formed over a second side of the semiconductor substrate, a fourth insulating layer formed over the third insulating layer, and a fifth insulating layer formed over the fourth insulating layer for incorporation in multi-stack package assemblies for reducing stress, strain, and/or warpage on the active elements within the package assembly.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: In some embodiments, the present disclosure relates to an image sensor including a substrate having a first side and a second side opposite the first side; a photodetector region within the substrate; a gate structure on the first side of the substrate over the photodetector region; a deep trench isolation (DTI) structure surrounding the photodetector region and extending from the first side of the substrate to the second side; a doped floating node region within the substrate at the first side and disposed between the gate structure and the DTI structure; and a floating node on the first side of the substrate, contacting a top surface of the DTI structure and overlying the doped floating node region.

Abstract: This disclosure provides methods, components, devices and systems for signal generation. Some aspects more specifically relate to frequency-selective digital predistortion signal generation. In some examples, the method alters an input signal to produce a frequency-selected linear output signal of a power amplifier. For frequency-selective pre-distortion signal generation, a digital pre-distortion circuit suppresses the non-linear distortion at a specific band using Volterra kernels of a Volterra series model and a shiftable finite impulse response (FIR). The shiftable FIR can filter a particular portion of the signal's frequency, and the Volterra kernels can capture the non-linear memory effects of the input signals and output signals of the power amplifier. Upon refinement of the Volterra kernel coefficients, the Volterra series model can produce a compensation signal.

Abstract: An optical element driving system is provided. The optical element driving system includes an optical element driving mechanism and a control assembly. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used for connecting to an optical element. The movable portion is movable relative to the fixed portion. The movable portion is in an accommodating space in the fixed portion. The driving assembly is used for driving the movable portion to move relative to the fixed portion. The control assembly provides a driving signal to the driving assembly to control the driving assembly. The driving assembly includes a first driving element, and the material of the first driving element includes shape memory alloy.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.