Patents by Inventor Jen-Cheng Liou

Jen-Cheng Liou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040130007
    Abstract: A lead semiconductor package includes a leadframe, a chip and an encapsulant. The leadframe has a central opening and multiple flat leads. The multiple flat leads define edges of the central opening. Each lead has an exposed portion and an inner thin portion. The inner thin portion is close to the central opening. The chip is mounted on the leads and is wire bonded to the inner thin portion. The inner thin portion is thicker than the exposed thick portion to provide a wire bonding space. Therefore, the semiconductor package is very thin. Further, the encapsulant covers the leadframe except portions of the leads and a portion of the chip to increase heat radiation.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Inventors: Cheng-Ho Hsu, Yi-Hua Chang, Jen-Cheng Liou
  • Patent number: 6703700
    Abstract: A semiconductor packaging structure mainly has a lead frame with a die pad and a plurality of leads, a wall portion formed by molding compound positioned around a periphery of the lead frame, a chip mounted on the die pad and electrically connected with the plurality of lead via gold wires, and a cover mounted on the wall portion to enclose the chip. An interval is defined between the die pad and the plurality of leads for filling with an isolating resin, the interval further communicates with multiple gaps and each gap is defined between two adjacent of the plurality of leads, wherein each gap is also filled with the isolating resin.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: March 9, 2004
    Inventors: Cheng-Ho Hsu, Yi-Hua Chang, Jen-Cheng Liou
  • Publication number: 20030071332
    Abstract: A semiconductor packaging structure mainly has a lead frame with a die pad and a plurality of leads, a wall portion formed by molding compound positioned around a periphery of the lead frame, a chip mounted on the die pad and electrically connected with the plurality of lead via gold wires, and a cover mounted on the wall portion to enclose the chip. An interval is defined between the die pad and the plurality of leads for filling with an isolating resin, the interval further communicates with multiple gaps and each gap is defined between two adjacent of the plurality of leads, wherein each gap is also filled with the isolating resin.
    Type: Application
    Filed: October 12, 2001
    Publication date: April 17, 2003
    Applicant: Taiwan IC Packaging Corporation
    Inventors: Cheng-Ho Hsu, Yi-Hua Chang, Jen-Cheng Liou